mirror of
https://github.com/AsahiLinux/u-boot
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d8f2aa3298
The AT32UC3A series of processors doesn't contain any cache, and issuing cache control instructions on those will cause an exception. This commit makes cacheflush.h arch-dependent in preparation for the AT32UC3A-support. Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com> Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com> Signed-off-by: Olav Morken <olavmrk@gmail.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
230 lines
5.2 KiB
C
230 lines
5.2 KiB
C
/*
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* Copyright (C) 2008 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
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#include <asm/arch/cacheflush.h>
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#include <asm/io.h>
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#include <asm/sections.h>
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DECLARE_GLOBAL_DATA_PTR;
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flash_info_t flash_info[1];
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static void flash_identify(uint16_t *flash, flash_info_t *info)
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{
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unsigned long flags;
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flags = disable_interrupts();
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dcache_flush_unlocked();
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writew(0xaa, flash + 0x555);
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writew(0x55, flash + 0xaaa);
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writew(0x90, flash + 0x555);
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info->flash_id = readl(flash);
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writew(0xff, flash);
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readw(flash);
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if (flags)
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enable_interrupts();
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}
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unsigned long flash_init(void)
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{
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unsigned long addr;
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unsigned int i;
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flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
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flash_info[0].sector_count = 135;
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flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
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for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
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flash_info[0].start[i] = addr;
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for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
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flash_info[0].start[i] = addr;
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return CONFIG_SYS_FLASH_SIZE;
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}
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void flash_print_info(flash_info_t *info)
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{
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printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
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info->flash_id >> 16, info->flash_id & 0xffff);
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printf("Size: %ld MB in %d sectors\n",
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info->size >> 10, info->sector_count);
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}
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int flash_erase(flash_info_t *info, int s_first, int s_last)
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{
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unsigned long flags;
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unsigned long start_time;
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uint16_t *fb, *sb;
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unsigned int i;
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int ret;
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uint16_t status;
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if ((s_first < 0) || (s_first > s_last)
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|| (s_last >= info->sector_count)) {
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puts("Error: first and/or last sector out of range\n");
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return ERR_INVAL;
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}
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for (i = s_first; i < s_last; i++)
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if (info->protect[i]) {
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printf("Error: sector %d is protected\n", i);
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return ERR_PROTECTED;
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}
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fb = (uint16_t *)uncached(info->start[0]);
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dcache_flush_unlocked();
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for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
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printf("Erasing sector %3d...", i);
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sb = (uint16_t *)uncached(info->start[i]);
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flags = disable_interrupts();
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start_time = get_timer(0);
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/* Unlock sector */
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writew(0xaa, fb + 0x555);
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writew(0x70, sb);
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/* Erase sector */
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writew(0xaa, fb + 0x555);
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writew(0x55, fb + 0xaaa);
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writew(0x80, fb + 0x555);
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writew(0xaa, fb + 0x555);
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writew(0x55, fb + 0xaaa);
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writew(0x30, sb);
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/* Wait for completion */
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ret = ERR_OK;
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do {
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/* TODO: Timeout */
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status = readw(sb);
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} while ((status != 0xffff) && !(status & 0x28));
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writew(0xf0, fb);
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/*
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* Make sure the command actually makes it to the bus
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* before we re-enable interrupts.
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*/
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readw(fb);
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if (flags)
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enable_interrupts();
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if (status != 0xffff) {
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printf("Flash erase error at address 0x%p: 0x%02x\n",
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sb, status);
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ret = ERR_PROG_ERROR;
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break;
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}
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}
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if (ctrlc())
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printf("User interrupt!\n");
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return ERR_OK;
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}
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int write_buff(flash_info_t *info, uchar *src,
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ulong addr, ulong count)
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{
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unsigned long flags;
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uint16_t *base, *p, *s, *end;
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uint16_t word, status, status1;
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int ret = ERR_OK;
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if (addr < info->start[0]
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|| (addr + count) > (info->start[0] + info->size)
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|| (addr + count) < addr) {
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puts("Error: invalid address range\n");
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return ERR_INVAL;
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}
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if (addr & 1 || count & 1 || (unsigned int)src & 1) {
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puts("Error: misaligned source, destination or count\n");
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return ERR_ALIGN;
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}
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base = (uint16_t *)uncached(info->start[0]);
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end = (uint16_t *)uncached(addr + count);
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flags = disable_interrupts();
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dcache_flush_unlocked();
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sync_write_buffer();
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for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
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p < end && !ctrlc(); p++, s++) {
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word = *s;
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writew(0xaa, base + 0x555);
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writew(0x55, base + 0xaaa);
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writew(0xa0, base + 0x555);
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writew(word, p);
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sync_write_buffer();
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/* Wait for completion */
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status1 = readw(p);
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do {
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/* TODO: Timeout */
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status = status1;
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status1 = readw(p);
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} while (((status ^ status1) & 0x40) /* toggled */
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&& !(status1 & 0x28)); /* error bits */
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/*
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* We'll need to check once again for toggle bit
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* because the toggle bit may stop toggling as I/O5
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* changes to "1" (ref at49bv642.pdf p9)
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*/
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status1 = readw(p);
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status = readw(p);
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if ((status ^ status1) & 0x40) {
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printf("Flash write error at address 0x%p: "
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"0x%02x != 0x%02x\n",
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p, status,word);
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ret = ERR_PROG_ERROR;
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writew(0xf0, base);
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readw(base);
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break;
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}
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writew(0xf0, base);
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readw(base);
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}
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if (flags)
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enable_interrupts();
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return ret;
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}
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#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */
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