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9bcb018870
This reverts commit c56ae7519f.
Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
Configuration Register (EVCR), Micron memories expect ALL commands to use
the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer
accepted.
Within the reverted commit, the write_evcr() function is implemented using
the spi_flash_write_common(), which is a shortcut for the
[ spi_flash_cmd_write_enable(), spi_flash_cmd_write(),
spi_flash_cmd_wait_ready() ] sequence.
Since the internal state of the Micron memory has been changed when the
spi_flash_cmd_write() function completes, the later call of the
spi_flash_cmd_wait_ready() function fails.
Indeed the SPI controller driver is not aware of the SPI protocol switch.
Further patches will fix the support of Micron QSPI memories.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
[Rebase on master, use JEDEC_MFR(info) in place of idcode0]
Signed-off-by: Jagan Teki <jagan@openedev.com>
228 lines
6.6 KiB
C
228 lines
6.6 KiB
C
/*
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* SPI flash internal definitions
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*
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* Copyright (C) 2008 Atmel Corporation
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* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SF_INTERNAL_H_
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#define _SF_INTERNAL_H_
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#include <linux/types.h>
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#include <linux/compiler.h>
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/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
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enum spi_dual_flash {
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SF_SINGLE_FLASH = 0,
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SF_DUAL_STACKED_FLASH = BIT(0),
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SF_DUAL_PARALLEL_FLASH = BIT(1),
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};
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enum spi_nor_option_flags {
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SNOR_F_SST_WR = BIT(0),
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SNOR_F_USE_FSR = BIT(1),
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SNOR_F_USE_UPAGE = BIT(3),
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};
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#define SPI_FLASH_3B_ADDR_LEN 3
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#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
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#define SPI_FLASH_16MB_BOUN 0x1000000
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/* CFI Manufacture ID's */
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#define SPI_FLASH_CFI_MFR_SPANSION 0x01
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#define SPI_FLASH_CFI_MFR_STMICRO 0x20
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#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
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#define SPI_FLASH_CFI_MFR_SST 0xbf
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#define SPI_FLASH_CFI_MFR_WINBOND 0xef
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#define SPI_FLASH_CFI_MFR_ATMEL 0x1f
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/* Erase commands */
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#define CMD_ERASE_4K 0x20
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#define CMD_ERASE_CHIP 0xc7
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#define CMD_ERASE_64K 0xd8
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/* Write commands */
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#define CMD_WRITE_STATUS 0x01
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#define CMD_PAGE_PROGRAM 0x02
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#define CMD_WRITE_DISABLE 0x04
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#define CMD_WRITE_ENABLE 0x06
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#define CMD_QUAD_PAGE_PROGRAM 0x32
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/* Read commands */
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#define CMD_READ_ARRAY_SLOW 0x03
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#define CMD_READ_ARRAY_FAST 0x0b
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#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
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#define CMD_READ_DUAL_IO_FAST 0xbb
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#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
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#define CMD_READ_QUAD_IO_FAST 0xeb
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#define CMD_READ_ID 0x9f
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#define CMD_READ_STATUS 0x05
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#define CMD_READ_STATUS1 0x35
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#define CMD_READ_CONFIG 0x35
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#define CMD_FLAG_STATUS 0x70
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/* Bank addr access commands */
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#ifdef CONFIG_SPI_FLASH_BAR
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# define CMD_BANKADDR_BRWR 0x17
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# define CMD_BANKADDR_BRRD 0x16
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# define CMD_EXTNADDR_WREAR 0xC5
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# define CMD_EXTNADDR_RDEAR 0xC8
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#endif
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/* Common status */
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#define STATUS_WIP BIT(0)
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#define STATUS_QEB_WINSPAN BIT(1)
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#define STATUS_QEB_MXIC BIT(6)
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#define STATUS_PEC BIT(7)
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#define SR_BP0 BIT(2) /* Block protect 0 */
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#define SR_BP1 BIT(3) /* Block protect 1 */
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#define SR_BP2 BIT(4) /* Block protect 2 */
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/* Flash timeout values */
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#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
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#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
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#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
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/* SST specific */
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#ifdef CONFIG_SPI_FLASH_SST
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# define CMD_SST_BP 0x02 /* Byte Program */
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# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
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int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
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const void *buf);
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int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
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const void *buf);
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#endif
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#define JEDEC_MFR(info) ((info)->id[0])
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#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
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#define JEDEC_EXT(info) (((info)->id[3]) << 8 | ((info)->id[4]))
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#define SPI_FLASH_MAX_ID_LEN 6
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struct spi_flash_info {
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/* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */
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const char *name;
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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u8 id[SPI_FLASH_MAX_ID_LEN];
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u8 id_len;
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/*
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* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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u32 sector_size;
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u32 n_sectors;
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u16 page_size;
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u16 flags;
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#define SECT_4K BIT(0) /* CMD_ERASE_4K works uniformly */
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#define E_FSR BIT(1) /* use flag status register for */
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#define SST_WR BIT(2) /* use SST byte/word programming */
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#define WR_QPP BIT(3) /* use Quad Page Program */
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#define RD_QUAD BIT(4) /* use Quad Read */
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#define RD_DUAL BIT(5) /* use Dual Read */
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#define RD_QUADIO BIT(6) /* use Quad IO Read */
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#define RD_DUALIO BIT(7) /* use Dual IO Read */
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#define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO)
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};
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extern const struct spi_flash_info spi_flash_ids[];
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/* Send a single-byte command to the device and read the response */
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int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
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/*
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* Send a multi-byte command to the device and read the response. Used
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* for flash array reads, etc.
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*/
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int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
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size_t cmd_len, void *data, size_t data_len);
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/*
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* Send a multi-byte command to the device followed by (optional)
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* data. Used for programming the flash array, etc.
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*/
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int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
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const void *data, size_t data_len);
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/* Flash erase(sectors) operation, support all possible erase commands */
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int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
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/* Lock stmicro spi flash region */
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int stm_lock(struct spi_flash *flash, u32 ofs, size_t len);
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/* Unlock stmicro spi flash region */
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int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len);
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/* Check if a stmicro spi flash region is completely locked */
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int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len);
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/* Enable writing on the SPI flash */
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static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
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{
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return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
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}
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/* Disable writing on the SPI flash */
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static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
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{
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return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
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}
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/*
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* Used for spi_flash write operation
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* - SPI claim
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* - spi_flash_cmd_write_enable
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* - spi_flash_cmd_write
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* - spi_flash_wait_till_ready
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* - SPI release
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*/
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int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
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size_t cmd_len, const void *buf, size_t buf_len);
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/*
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* Flash write operation, support all possible write commands.
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* Write the requested data out breaking it up into multiple write
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* commands as needed per the write size.
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*/
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int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
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size_t len, const void *buf);
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/*
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* Same as spi_flash_cmd_read() except it also claims/releases the SPI
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* bus. Used as common part of the ->read() operation.
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*/
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int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
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size_t cmd_len, void *data, size_t data_len);
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/* Flash read operation, support all possible read commands */
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int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
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size_t len, void *data);
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#ifdef CONFIG_SPI_FLASH_MTD
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int spi_flash_mtd_register(struct spi_flash *flash);
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void spi_flash_mtd_unregister(void);
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#endif
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/**
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* spi_flash_scan - scan the SPI FLASH
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* @flash: the spi flash structure
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*
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* The drivers can use this fuction to scan the SPI FLASH.
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* In the scanning, it will try to get all the necessary information to
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* fill the spi_flash{}.
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*
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* Return: 0 for success, others for failure.
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*/
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int spi_flash_scan(struct spi_flash *flash);
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#endif /* _SF_INTERNAL_H_ */
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