u-boot/doc/device-tree-bindings/clock
Patrick Delaunay 37ad8377af stm32mp1: clk: configure pll1 with OPP
The PLL1 node (st,pll1) is optional in device tree, the max supported
frequency define in OPP node is used when the node is absent.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
..
fixed-factor-clock.txt clk: Add fixed-factor clock driver 2019-02-27 09:12:33 +08:00
fsl,mpc83xx-clk.txt doc: Remove duplicated documentation directory 2019-06-20 10:57:08 -04:00
microchip,pic32-clock.txt
nvidia,tegra20-car.txt
rockchip,rk3188-cru.txt
rockchip,rk3288-cru.txt
rockchip,rk3288-dmc.txt
rockchip,rk3368-dmc.txt rockchip: rk3368: add DRAM controller driver with DRAM initialisation 2017-08-13 17:12:33 +02:00
rockchip,rk3399-dmc.txt
rockchip.txt
snps,hsdk-cgu.txt ARC: clk: introduce HSDK CGU clock driver 2017-12-11 11:36:23 +03:00
st,stm32-rcc.txt
st,stm32h7-rcc.txt dm: clk: add clk driver support for stm32h7 SoCs 2017-09-22 07:40:01 -04:00
st,stm32mp1.txt stm32mp1: clk: configure pll1 with OPP 2020-07-07 16:01:23 +02:00
ti,cdce9xx.txt clk: cdce9xx: add support for cdce9xx clock synthesizer 2019-10-11 13:32:39 -04:00
ti,sci-clk.txt clk: Introduce TI System Control Interface (TI SCI) clock driver 2018-09-11 08:32:55 -04:00