mirror of
https://github.com/AsahiLinux/u-boot
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f57f35a833
RK3288 using the dwc2 USB host controller, enable it and other usb host funtion like storage and ether. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Added rockchip: tag: Signed-off-by: Simon Glass <sjg@chromium.org>
120 lines
3.1 KiB
C
120 lines
3.1 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_RK3288_COMMON_H
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#define __CONFIG_RK3288_COMMON_H
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#include <asm/arch/hardware.h>
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#include "rockchip-common.h"
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#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_THUMB_BUILD
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#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
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#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_SPL_BOARD_INIT
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#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
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/* Bootrom will load u-boot binary to 0x0 once return from SPL */
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x00100000
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#endif
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#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SPL_STACK 0xff718000
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#define CONFIG_SPL_TEXT_BASE 0xff704004
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/* MMC/SD IP block */
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#define CONFIG_GENERIC_MMC
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_FAT_WRITE
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#define CONFIG_PARTITION_UUIDS
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#define CONFIG_CMD_PART
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/* RAW SD card / eMMC locations. */
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
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/* FAT sd card locations. */
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SYS_SDRAM_BASE 0
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#define CONFIG_NR_DRAM_BANKS 1
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#define SDRAM_BANK_SIZE (2UL << 30)
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#ifndef CONFIG_SPL_BUILD
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/* usb otg */
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#define CONFIG_USB_GADGET
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#define CONFIG_USB_GADGET_DUALSPEED
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#define CONFIG_USB_GADGET_DWC2_OTG
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#define CONFIG_ROCKCHIP_USB2_PHY
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#define CONFIG_USB_GADGET_VBUS_DRAW 0
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/* fastboot */
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#define CONFIG_CMD_FASTBOOT
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#define CONFIG_USB_FUNCTION_FASTBOOT
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#define CONFIG_FASTBOOT_FLASH
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#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */
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#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
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#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000
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/* usb mass storage */
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#define CONFIG_USB_FUNCTION_MASS_STORAGE
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#define CONFIG_CMD_USB_MASS_STORAGE
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#define CONFIG_USB_GADGET_DOWNLOAD
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#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
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#define CONFIG_G_DNL_VENDOR_NUM 0x2207
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#define CONFIG_G_DNL_PRODUCT_NUM 0x320a
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/* usb host support */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_DWC2
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_SMSC95XX
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#define CONFIG_USB_ETHER_ASIX
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#endif
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00000000\0" \
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"pxefile_addr_r=0x00100000\0" \
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"fdt_addr_r=0x01f00000\0" \
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"kernel_addr_r=0x02000000\0" \
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"ramdisk_addr_r=0x04000000\0"
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#include <config_distro_bootcmd.h>
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/* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so
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* limit the fdt reallocation to that */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x0fffffff\0" \
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"initrd_high=0x0fffffff\0" \
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"partitions=" PARTS_DEFAULT \
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ENV_MEM_LAYOUT_SETTINGS \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_PREBOOT
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#endif
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