mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
9fbb0c3aa4
There are 2 reasons for doing this:
1) The main reason for doing this is to move it outside of
board/sunxi/ahci.c, so that it can be used on boards which use
a usb<->sata chip too;
2) While doing this I realized that doing it from board_init also meant
doing it much earlier. Some printf get_timer(0) calls show that the
time between board_init() and scsi_init() is more then 600 ms,
so we can drop the mdelay(500)
While at it also drop the printf("SUNXI SCSI INIT\n") AHCI init is
noisy enough by itself.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
79 lines
1.8 KiB
C
79 lines
1.8 KiB
C
#include <common.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#define AHCI_PHYCS0R 0x00c0
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#define AHCI_PHYCS1R 0x00c4
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#define AHCI_PHYCS2R 0x00c8
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#define AHCI_RWCR 0x00fc
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/* This magic PHY initialisation was taken from the Allwinner releases
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* and Linux driver, but is completely undocumented.
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*/
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static int sunxi_ahci_phy_init(u32 base)
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{
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u8 *reg_base = (u8 *)base;
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u32 reg_val;
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int timeout;
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writel(0, reg_base + AHCI_RWCR);
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mdelay(5);
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setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
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clrsetbits_le32(reg_base + AHCI_PHYCS0R,
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(0x7 << 24),
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(0x5 << 24) | (0x1 << 23) | (0x1 << 18));
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clrsetbits_le32(reg_base + AHCI_PHYCS1R,
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(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
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(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
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setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
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clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
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clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
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clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
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mdelay(5);
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setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
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timeout = 250; /* Power up takes approx 50 us */
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for (;;) {
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reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
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if (reg_val == (0x2 << 28))
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break;
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if (--timeout == 0) {
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printf("AHCI PHY power up failed.\n");
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return -EIO;
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}
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udelay(1);
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};
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setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
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timeout = 100; /* Calibration takes approx 10 us */
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for (;;) {
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reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
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if (reg_val == 0x0)
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break;
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if (--timeout == 0) {
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printf("AHCI PHY calibration failed.\n");
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return -EIO;
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}
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udelay(1);
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}
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mdelay(15);
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writel(0x7, reg_base + AHCI_RWCR);
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return 0;
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}
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void scsi_init(void)
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{
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if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
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return;
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ahci_init((void __iomem *)SUNXI_SATA_BASE);
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}
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