u-boot/board/qca/ap143/Kconfig
Paul Burton 372286217f MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:44:24 +02:00

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if TARGET_AP143
config SYS_VENDOR
default "qca"
config SYS_BOARD
default "ap143"
config SYS_CONFIG_NAME
default "ap143"
config SYS_TEXT_BASE
default 0x9f000000
config SYS_DCACHE_SIZE
default 32768
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 65536
config SYS_ICACHE_LINE_SIZE
default 32
endif