mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
8c103c33fb
Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
188 lines
2.5 KiB
Text
188 lines
2.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright 2022 Toradex
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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bootph-pre-ram;
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wdt = <&wdog1>;
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};
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};
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&{/aliases} {
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eeprom0 = &eeprom_module;
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eeprom1 = &eeprom_carrier_board;
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eeprom2 = &eeprom_display_adapter;
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};
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&clk {
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bootph-all;
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bootph-pre-ram;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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};
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&crypto {
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bootph-pre-ram;
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};
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&eqos {
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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regulator-ethphy {
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gpio-hog;
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gpios = <20 GPIO_ACTIVE_HIGH>;
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line-name = "reg_ethphy";
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output-high;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_eth>;
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};
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};
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&gpio3 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&i2c1 {
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bootph-pre-ram;
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eeprom_module: eeprom@50 {
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compatible = "i2c-eeprom";
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pagesize = <16>;
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reg = <0x50>;
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};
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};
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&i2c2 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&i2c4 {
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/* EEPROM on display adapter (MIPI DSI Display Adapter) */
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eeprom_display_adapter: eeprom@50 {
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compatible = "i2c-eeprom";
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pagesize = <16>;
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reg = <0x50>;
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};
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/* EEPROM on carrier board */
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eeprom_carrier_board: eeprom@57 {
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compatible = "i2c-eeprom";
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pagesize = <16>;
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reg = <0x57>;
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};
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};
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&pca9450 {
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bootph-pre-ram;
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};
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&pinctrl_i2c1 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_pwr_en {
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bootph-pre-ram;
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u-boot,off-on-delay-us = <20000>;
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};
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&pinctrl_uart3 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_cd {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_wdog {
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bootph-pre-ram;
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};
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®_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&sec_jr0 {
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bootph-pre-ram;
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};
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&sec_jr1 {
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bootph-pre-ram;
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};
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&sec_jr2 {
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bootph-pre-ram;
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};
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&uart3 {
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bootph-pre-ram;
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};
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&usdhc1 {
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status = "disabled";
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};
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&usdhc2 {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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assigned-clock-rates = <400000000>;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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sd-uhs-ddr50;
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sd-uhs-sdr104;
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bootph-pre-ram;
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};
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&usdhc3 {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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assigned-clock-rates = <400000000>;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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bootph-pre-ram;
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};
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&wdog1 {
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bootph-pre-ram;
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};
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