mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 19:02:12 +00:00
e5703df262
BCM4908 is a Broadcom B53 based WLAN AP router SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family so it's added under ARCH_BCMBCA platform. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory and Broadcom uart. This SoC is supported in the linux git repository so the dts and dtsi files are stripped down version of linux copies with mininum blocks needed by u-boot. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
127 lines
2.7 KiB
Text
127 lines
2.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
compatible = "brcm,bcm4908", "brcm,bcmbca";
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "brcm,brahma-b53";
|
|
reg = <0x0>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0xfff8>;
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "brcm,brahma-b53";
|
|
reg = <0x1>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0xfff8>;
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "brcm,brahma-b53";
|
|
reg = <0x2>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0xfff8>;
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "brcm,brahma-b53";
|
|
reg = <0x3>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0xfff8>;
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
l2: l2-cache0 {
|
|
compatible = "cache";
|
|
};
|
|
};
|
|
|
|
axi@81000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00 0x00 0x81000000 0x4000>;
|
|
|
|
gic: interrupt-controller@1000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x1000 0x1000>,
|
|
<0x2000 0x2000>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a53-pmu";
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
|
};
|
|
|
|
clocks {
|
|
periph_clk: periph_clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <50000000>;
|
|
clock-output-names = "periph";
|
|
};
|
|
};
|
|
|
|
bus@ff800000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00 0x00 0xff800000 0x3000>;
|
|
|
|
uart0: serial@640 {
|
|
compatible = "brcm,bcm6345-uart";
|
|
reg = <0x640 0x18>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&periph_clk>;
|
|
clock-names = "refclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
};
|