mirror of
https://github.com/AsahiLinux/u-boot
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411 lines
15 KiB
C
411 lines
15 KiB
C
/*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
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#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
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#define CONFIG_CPCI405AB 1 /* ...and special AB version */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#undef CONFIG_BOOTARGS
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_PREBOOT /* enable preboot variable */
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#undef CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_EEPROM
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SUPPORT_VFAT
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#undef CFG_HUSH_PARSER /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
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#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
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#define CFG_BASE_BAUD 691200
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
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#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
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#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
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#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
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#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
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#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
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#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
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#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
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#define CFG_ATA_BASE_ADDR 0xF0100000
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
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#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFFFC0000
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
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#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
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#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
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/*
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* The following defines are added for buggy IOP480 byte interface.
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* All other boards should use the standard values (CPCI405 etc.)
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*/
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#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
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#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
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#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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/*
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* JFFS2 partitions
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*/
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/* No command line, one static partition */
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#undef CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nor0"
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/* Use first bank for JFFS2, second bank contains U-Boot.
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*
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* Note: fake mtd_id's used, no linux mtd map file.
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*/
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/*
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=cpci405ab-0"
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#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)"
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*/
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/*-----------------------------------------------------------------------
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* I2C EEPROM (CAT24WC32) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
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#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
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#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */
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#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
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/* 32 byte page write mode using*/
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/* last 5 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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/* Use EEPROM for environment variables */
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
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#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
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/* total size of a CAT24WC32 is 4096 bytes */
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#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
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#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
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#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
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/* have only 8kB, 16kB is save here */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*/
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/* Memory Bank 0 (Flash Bank 0) initialization */
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#define CFG_EBC_PB0AP 0x92015480
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#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
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/* Memory Bank 1 (Flash Bank 1) initialization */
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#define CFG_EBC_PB1AP 0x92015480
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#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
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/* Memory Bank 2 (CAN0, 1) initialization */
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#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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#define CFG_LED_ADDR 0xF0000380
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/* Memory Bank 3 (CompactFlash IDE) initialization */
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#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
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/* Memory Bank 4 (NVRAM/RTC) initialization */
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/*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
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#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
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#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 5 (optional Quart) initialization */
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#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
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#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 6 (FPGA internal) initialization */
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#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
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#define CFG_FPGA_BASE_ADDR 0xF0400000
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/*-----------------------------------------------------------------------
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* FPGA stuff
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*/
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/* FPGA internal regs */
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#define CFG_FPGA_MODE 0x00
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#define CFG_FPGA_STATUS 0x02
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#define CFG_FPGA_TS 0x04
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#define CFG_FPGA_TS_LOW 0x06
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#define CFG_FPGA_TS_CAP0 0x10
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#define CFG_FPGA_TS_CAP0_LOW 0x12
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#define CFG_FPGA_TS_CAP1 0x14
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#define CFG_FPGA_TS_CAP1_LOW 0x16
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#define CFG_FPGA_TS_CAP2 0x18
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#define CFG_FPGA_TS_CAP2_LOW 0x1a
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#define CFG_FPGA_TS_CAP3 0x1c
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#define CFG_FPGA_TS_CAP3_LOW 0x1e
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/* FPGA Mode Reg */
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#define CFG_FPGA_MODE_CF_RESET 0x0001
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#define CFG_FPGA_MODE_DUART_RESET 0x0002
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#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
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#define CFG_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */
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#define CFG_FPGA_MODE_SIM_OK_DIR 0x0200
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#define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
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#define CFG_FPGA_MODE_1WIRE 0x1000
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#define CFG_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */
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#define CFG_FPGA_MODE_TESTRIG_FAIL 0x4000
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/* FPGA Status Reg */
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#define CFG_FPGA_STATUS_DIP0 0x0001
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#define CFG_FPGA_STATUS_DIP1 0x0002
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#define CFG_FPGA_STATUS_DIP2 0x0004
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#define CFG_FPGA_STATUS_FLASH 0x0008
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#define CFG_FPGA_STATUS_1WIRE 0x1000
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#define CFG_FPGA_STATUS_SIM_OK 0x2000
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#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
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#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */
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/* FPGA program pin configuration */
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#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
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#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
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#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
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#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
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#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
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#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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