mirror of
https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
87 lines
2.2 KiB
C
87 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2003
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* Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <asm/global_data.h>
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#include <asm/processor.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
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int get_clocks(void)
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{
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#if defined(CONFIG_M5208)
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pll_t *pll = (pll_t *) MMAP_PLL;
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out_8(&pll->odr, CFG_SYS_PLL_ODR);
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out_8(&pll->fdr, CFG_SYS_PLL_FDR);
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#endif
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
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volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
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unsigned long pllcr;
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#ifndef CFG_SYS_PLL_BYPASS
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#ifdef CONFIG_M5249
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/* Setup the PLL to run at the specified speed */
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#ifdef CFG_SYS_FAST_CLK
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pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
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#else
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pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
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#endif
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#endif /* CONFIG_M5249 */
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#ifdef CONFIG_M5253
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pllcr = CFG_SYS_PLLCR;
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#endif /* CONFIG_M5253 */
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cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
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mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
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pllcr ^= 0x00000001; /* Set pll bypass to 1 */
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
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udelay(0x20); /* Wait for a lock ... */
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#endif /* #ifndef CFG_SYS_PLL_BYPASS */
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#endif /* CONFIG_M5249 || CONFIG_M5253 */
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#if defined(CONFIG_M5275)
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pll_t *pll = (pll_t *)(MMAP_PLL);
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/* Setup PLL */
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out_be32(&pll->syncr, 0x01080000);
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while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
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;
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out_be32(&pll->syncr, 0x01000000);
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while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
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;
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#endif
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gd->cpu_clk = CFG_SYS_CLK;
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#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
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defined(CONFIG_M5271) || defined(CONFIG_M5275)
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gd->bus_clk = gd->cpu_clk / 2;
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#else
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gd->bus_clk = gd->cpu_clk;
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#endif
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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#ifdef CONFIG_SYS_I2C2_FSL_OFFSET
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gd->arch.i2c2_clk = gd->bus_clk;
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#endif
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#endif
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return (0);
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}
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