mirror of
https://github.com/AsahiLinux/u-boot
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29caf9305b
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
400 lines
9.7 KiB
C
400 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <div64.h>
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#include <fdtdec.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <reset.h>
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#include "sdram_soc64.h"
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#include <wait_bit.h>
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#include <asm/arch/firewall.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/sizes.h>
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#define PGTABLE_OFF 0x4000
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u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
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{
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return readl(plat->iomhc + reg);
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}
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u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg)
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{
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return readl(plat->hmc + reg);
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}
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u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
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u32 data, u32 reg)
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{
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return writel(data, plat->hmc + reg);
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}
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u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
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u32 reg)
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{
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return writel(data, plat->ddr_sch + reg);
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}
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int emif_clear(struct altera_sdram_plat *plat)
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{
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hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
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return wait_for_bit_le32((const void *)(plat->hmc +
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RSTHANDSHAKESTAT),
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DDR_HMC_RSTHANDSHAKE_MASK,
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false, 1000, false);
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}
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int emif_reset(struct altera_sdram_plat *plat)
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{
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u32 c2s, s2c, ret;
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c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
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s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
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debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
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c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
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hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
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hmc_readl(plat, DRAMSTS));
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if (s2c && emif_clear(plat)) {
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printf("DDR: emif_clear() failed\n");
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return -1;
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}
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debug("DDR: Triggerring emif reset\n");
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hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
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/* if seq2core[3] = 0, we are good */
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ret = wait_for_bit_le32((const void *)(plat->hmc +
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RSTHANDSHAKESTAT),
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DDR_HMC_SEQ2CORE_INT_RESP_MASK,
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false, 1000, false);
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if (ret) {
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printf("DDR: failed to get ack from EMIF\n");
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return ret;
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}
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ret = emif_clear(plat);
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if (ret) {
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printf("DDR: emif_clear() failed\n");
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return ret;
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}
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debug("DDR: %s triggered successly\n", __func__);
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return 0;
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}
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#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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int poll_hmc_clock_status(void)
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{
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return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
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SYSMGR_SOC64_HMC_CLK),
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SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
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}
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#endif
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void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
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{
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phys_size_t i;
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if (addr % CONFIG_SYS_CACHELINE_SIZE) {
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printf("DDR: address 0x%llx is not cacheline size aligned.\n",
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addr);
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hang();
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}
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if (size % CONFIG_SYS_CACHELINE_SIZE) {
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printf("DDR: size 0x%llx is not multiple of cacheline size\n",
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size);
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hang();
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}
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/* Use DC ZVA instruction to clear memory to zeros by a cache line */
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for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
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asm volatile("dc zva, %0"
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:
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: "r"(addr)
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: "memory");
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addr += CONFIG_SYS_CACHELINE_SIZE;
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}
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}
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void sdram_init_ecc_bits(struct bd_info *bd)
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{
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phys_size_t size, size_init;
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phys_addr_t start_addr;
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int bank = 0;
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unsigned int start = get_timer(0);
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icache_enable();
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start_addr = bd->bi_dram[0].start;
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size = bd->bi_dram[0].size;
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/* Initialize small block for page table */
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memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
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gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
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gd->arch.tlb_size = PGTABLE_SIZE;
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start_addr += PGTABLE_SIZE + PGTABLE_OFF;
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size -= (PGTABLE_OFF + PGTABLE_SIZE);
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dcache_enable();
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while (1) {
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while (size) {
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size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
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sdram_clear_mem(start_addr, size_init);
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size -= size_init;
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start_addr += size_init;
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schedule();
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}
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bank++;
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if (bank >= CONFIG_NR_DRAM_BANKS)
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break;
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start_addr = bd->bi_dram[bank].start;
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size = bd->bi_dram[bank].size;
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}
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dcache_disable();
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icache_disable();
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printf("SDRAM-ECC: Initialized success with %d ms\n",
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(unsigned int)get_timer(start));
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}
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void sdram_size_check(struct bd_info *bd)
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{
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phys_size_t total_ram_check = 0;
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phys_size_t ram_check = 0;
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phys_addr_t start = 0;
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phys_size_t size, remaining_size;
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int bank;
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/* Sanity check ensure correct SDRAM size specified */
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debug("DDR: Running SDRAM size sanity check\n");
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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start = bd->bi_dram[bank].start;
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remaining_size = bd->bi_dram[bank].size;
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while (ram_check < bd->bi_dram[bank].size) {
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size = min((phys_addr_t)SZ_1G,
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(phys_addr_t)remaining_size);
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/*
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* Ensure the size is power of two, this is requirement
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* to run get_ram_size() / memory test
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*/
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if (size != 0 && ((size & (size - 1)) == 0)) {
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ram_check += get_ram_size((void *)
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(start + ram_check), size);
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remaining_size = bd->bi_dram[bank].size -
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ram_check;
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} else {
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puts("DDR: Memory test requires SDRAM size ");
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puts("in power of two!\n");
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hang();
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}
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}
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total_ram_check += ram_check;
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ram_check = 0;
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}
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/* If the ram_size is 2GB smaller, we can assume the IO space is
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* not mapped in. gd->ram_size is the actual size of the dram
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* not the accessible size.
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*/
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if (total_ram_check != gd->ram_size) {
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puts("DDR: SDRAM size check failed!\n");
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hang();
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}
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debug("DDR: SDRAM size check passed!\n");
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}
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/**
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* sdram_calculate_size() - Calculate SDRAM size
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*
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* Calculate SDRAM device size based on SDRAM controller parameters.
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* Size is specified in bytes.
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*/
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phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
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{
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u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
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phys_size_t size = (phys_size_t)1 <<
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(DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
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size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
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DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
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return size;
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}
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void sdram_set_firewall(struct bd_info *bd)
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{
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u32 i;
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phys_size_t value;
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u32 lower, upper;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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if (!bd->bi_dram[i].size)
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continue;
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value = bd->bi_dram[i].start;
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/* Keep first 1MB of SDRAM memory region as secure region when
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* using ATF flow, where the ATF code is located.
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*/
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if (IS_ENABLED(CONFIG_SPL_ATF) && i == 0)
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value += SZ_1M;
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/* Setting non-secure MPU region base and base extended */
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lower = lower_32_bits(value);
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upper = upper_32_bits(value);
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FW_MPU_DDR_SCR_WRITEL(lower,
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FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE +
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(i * 4 * sizeof(u32)));
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FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
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FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT +
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(i * 4 * sizeof(u32)));
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/* Setting non-secure Non-MPU region base and base extended */
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FW_MPU_DDR_SCR_WRITEL(lower,
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FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE +
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(i * 4 * sizeof(u32)));
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FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
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FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT +
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(i * 4 * sizeof(u32)));
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/* Setting non-secure MPU limit and limit extexded */
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value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
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lower = lower_32_bits(value);
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upper = upper_32_bits(value);
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FW_MPU_DDR_SCR_WRITEL(lower,
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FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT +
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(i * 4 * sizeof(u32)));
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FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
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FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT +
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(i * 4 * sizeof(u32)));
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/* Setting non-secure Non-MPU limit and limit extexded */
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FW_MPU_DDR_SCR_WRITEL(lower,
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FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT +
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(i * 4 * sizeof(u32)));
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FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
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FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT +
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(i * 4 * sizeof(u32)));
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FW_MPU_DDR_SCR_WRITEL(BIT(i) | BIT(i + 8),
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FW_MPU_DDR_SCR_EN_SET);
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}
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}
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static int altera_sdram_of_to_plat(struct udevice *dev)
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{
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struct altera_sdram_plat *plat = dev_get_plat(dev);
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fdt_addr_t addr;
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/* These regs info are part of DDR handoff in bitstream */
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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return 0;
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#endif
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addr = dev_read_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->ddr_sch = (void __iomem *)addr;
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addr = dev_read_addr_index(dev, 1);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->iomhc = (void __iomem *)addr;
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addr = dev_read_addr_index(dev, 2);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->hmc = (void __iomem *)addr;
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return 0;
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}
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static int altera_sdram_probe(struct udevice *dev)
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{
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int ret;
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struct altera_sdram_priv *priv = dev_get_priv(dev);
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ret = reset_get_bulk(dev, &priv->resets);
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if (ret) {
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dev_err(dev, "Can't get reset: %d\n", ret);
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return -ENODEV;
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}
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reset_deassert_bulk(&priv->resets);
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if (sdram_mmr_init_full(dev) != 0) {
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puts("SDRAM init failed.\n");
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goto failed;
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}
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return 0;
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failed:
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reset_release_bulk(&priv->resets);
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return -ENODEV;
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}
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static int altera_sdram_get_info(struct udevice *dev,
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struct ram_info *info)
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{
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struct altera_sdram_priv *priv = dev_get_priv(dev);
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info->base = priv->info.base;
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info->size = priv->info.size;
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return 0;
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}
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static struct ram_ops altera_sdram_ops = {
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.get_info = altera_sdram_get_info,
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};
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static const struct udevice_id altera_sdram_ids[] = {
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{ .compatible = "altr,sdr-ctl-s10" },
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{ .compatible = "intel,sdr-ctl-agilex" },
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{ .compatible = "intel,sdr-ctl-n5x" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(altera_sdram) = {
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.name = "altr_sdr_ctl",
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.id = UCLASS_RAM,
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.of_match = altera_sdram_ids,
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.ops = &altera_sdram_ops,
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.of_to_plat = altera_sdram_of_to_plat,
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.plat_auto = sizeof(struct altera_sdram_plat),
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.probe = altera_sdram_probe,
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.priv_auto = sizeof(struct altera_sdram_priv),
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};
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