Quentin Schulz 23b71addf9 rockchip: clk: add watchdog clock to px30_clk_enable ... Add the PCLK_WDT_NS clock to px30_clk_enable so that the watchdog driver can probe since it wants to enable this clock. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>		2023-01-16 18:01:10 +08:00
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clk_pll.c	rockchip: clk: pll: Fix constant typo	2022-10-19 12:06:48 -04:00
clk_px30.c	rockchip: clk: add watchdog clock to px30_clk_enable	2023-01-16 18:01:10 +08:00
clk_rk322x.c	dm: Use access methods for dev/uclass private data	2021-01-05 12:24:40 -07:00
clk_rk3036.c	dm: Use access methods for dev/uclass private data	2021-01-05 12:24:40 -07:00
clk_rk3066.c	rockchip: rk3066: add clock driver for rk3066 soc	2022-04-18 11:25:13 +08:00
clk_rk3128.c	rockchip: rk3128-cru: sync the clock dt-binding header from Linux	2022-12-19 10:56:12 +08:00
clk_rk3188.c	treewide: Try to avoid the preprocessor with OF_REAL	2021-09-25 09:46:15 -06:00
clk_rk3288.c	treewide: Try to avoid the preprocessor with OF_REAL	2021-09-25 09:46:15 -06:00
clk_rk3308.c	treewide: Simply conditions with the new OF_REAL	2021-09-25 09:46:15 -06:00
clk_rk3328.c	dm: Use access methods for dev/uclass private data	2021-01-05 12:24:40 -07:00
clk_rk3368.c	treewide: Try to avoid the preprocessor with OF_REAL	2021-09-25 09:46:15 -06:00
clk_rk3399.c	arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented range	2022-10-19 19:30:48 +08:00
clk_rk3568.c	clk: rockchip: rk3568: update clks	2021-10-15 20:57:31 +08:00
clk_rv1108.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
Makefile	rockchip: rk3066: add clock driver for rk3066 soc	2022-04-18 11:25:13 +08:00