u-boot/board/freescale/mpc8568mds
York Sun 316f0d0f8f powerpc: mpc85xx: Fix static TLB table for SDRAM
Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-12-06 14:54:12 -08:00
..
bcsr.c Coding Style cleanup: remove trailing white space 2013-10-14 16:06:53 -04:00
bcsr.h Coding Style cleanup: remove trailing white space 2013-10-14 16:06:53 -04:00
ddr.c Add more SPDX-License-Identifier tags 2016-01-19 08:31:21 -05:00
Kconfig kconfig: remove redundant "string" type in arch and board Kconfigs 2014-09-13 16:43:55 -04:00
law.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
MAINTAINERS powerpc: mpc8568mds: Update board config 2017-06-12 12:18:37 -07:00
Makefile board: powerpc: convert makefiles to Kbuild style 2013-11-01 11:42:12 -04:00
mpc8568mds.c fdt: Allow ft_board_setup() to report failure 2014-11-21 04:43:15 +01:00
tlb.c powerpc: mpc85xx: Fix static TLB table for SDRAM 2017-12-06 14:54:12 -08:00