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aa6e94deab
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
91 lines
2 KiB
C
91 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2020 Hitachi Power Grids. All rights reserved.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/global_data.h>
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#include <asm/arch/ls102xa_soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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if (ctrl_num > 1) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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// 1/2 DRAM cycle (should be increased in case of ADDR/CMD heavily loaded than the clock)
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popts->clk_adjust = 0x4;
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popts->write_data_delay = 0x4;
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// wr leveling start value for lane 0
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popts->wrlvl_start = 0x5;
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// wr leveling start values for lanes 1-3 (lane 4 not there)
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popts->wrlvl_ctl_2 = 0x05050500;
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// 32-bit DRAM, no need to set start values for lanes we do not have (5-8)
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popts->wrlvl_ctl_3 = 0x0;
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popts->cpo_override = 0x1f;
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/* force DDR bus width to 32 bits */
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popts->data_bus_width = 1;
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popts->otf_burst_chop_en = 0;
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popts->burst_length = DDR_BL8;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 1;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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popts->cswl_override = DDR_CSWL_CS0;
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/* optimize cpo for erratum A-009942 */
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popts->cpo_sample = 0x58;
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/* DHC_EN =1, ODT = 75 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
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}
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int fsl_initdram(void)
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{
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phys_size_t dram_size;
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puts("Initializing DDR....using SPD\n");
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dram_size = fsl_ddr_sdram();
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erratum_a008850_post();
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gd->ram_size = dram_size;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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