mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
2c808a12ea
The last users of CONFIG_KGDB_SER_INDEX were removed more than 3 years ago in commits550650ddd0andbf16500f79, either kgdb subsystem should care about this parameter or it should be gone completely. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
336 lines
9.2 KiB
C
336 lines
9.2 KiB
C
/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Copied from lubbock.h
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*
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* (C) Copyright 2004
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* BEC Systems <http://bec-systems.com>
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* Cliff Brake <cliff.brake@gmail.com>
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* Configuation settings for the Accelent/Vibren PXA255 IDP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/pxa-regs.h>
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/*
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* If we are developing, we might want to start U-Boot from RAM
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* so we MUST NOT initialize critical regs like mem-timing ...
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*/
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#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
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#define CONFIG_SYS_TEXT_BASE 0x0
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/*
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* define the following to enable debug blinks. A debug blink function
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* must be defined in memsetup.S
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*/
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#undef DEBUG_BLINK_ENABLE
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#undef DEBUG_BLINKC_ENABLE
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
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#undef CONFIG_LCD
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#ifdef CONFIG_LCD
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#define CONFIG_PXA_LCD
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#define CONFIG_SHARP_LM8V31
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#endif
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#define CONFIG_MMC 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_BOARD_LATE_INIT
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/*
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* PXA250 IDP memory map information
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*/
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#define IDP_CS5_ETH_OFFSET 0x03400000
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/*
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* Hardware drivers
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*/
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#define CONFIG_SMC91111
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#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
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#define CONFIG_SMC_USE_32_BIT 1
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/* #define CONFIG_SMC_USE_IOFUNCS */
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/* the following has to be set high -- suspect something is wrong with
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* with the tftp timeout routines. FIXME!!!
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*/
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#define CONFIG_NET_RETRY_COUNT 100
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/*
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* select serial console configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
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#define CONFIG_CONS_INDEX 3
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_DHCP
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTCOMMAND "bootm 40000"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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/* #define CONFIG_INITRD_TAG 1 */
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/*
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* Current memory map for Vibren supplied Linux images:
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*
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* Flash:
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* 0 - 0x3ffff (size = 0x40000): bootloader
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* 0x40000 - 0x13ffff (size = 0x100000): kernel
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* 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
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*
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* RAM:
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* 0xa0008000 - kernel is loaded
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* 0xa3000000 - Uboot runs (48MB into RAM)
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*
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"prog_boot_mmc=" \
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"mw.b 0xa0000000 0xff 0x40000; " \
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"if mmcinit && " \
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"fatload mmc 0 0xa0000000 u-boot.bin; " \
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"then " \
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"protect off 0x0 0x3ffff; " \
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"erase 0x0 0x3ffff; " \
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"cp.b 0xa0000000 0x0 0x40000; " \
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"reset;" \
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"fi\0" \
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"prog_uzImage_mmc=" \
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"mw.b 0xa0000000 0xff 0x100000; " \
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"if mmcinit && " \
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"fatload mmc 0 0xa0000000 uzImage; " \
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"then " \
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"protect off 0x40000 0xfffff; " \
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"erase 0x40000 0xfffff; " \
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"cp.b 0xa0000000 0x40000 0x100000; " \
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"fi\0" \
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"prog_jffs_mmc=" \
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"mw.b 0xa0000000 0xff 0x1e00000; " \
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"if mmcinit && " \
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"fatload mmc 0 0xa0000000 root.jffs; " \
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"then " \
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"protect off 0x140000 0x1f3ffff; " \
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"erase 0x140000 0x1f3ffff; " \
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"cp.b 0xa0000000 0x140000 0x1e00000; " \
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"fi\0" \
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"boot_mmc=" \
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"if mmcinit && " \
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"fatload mmc 0 0xa1000000 uzImage && " \
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"then " \
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"bootm 0xa1000000; " \
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"fi\0" \
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"prog_boot_net=" \
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"mw.b 0xa0000000 0xff 0x100000; " \
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"if bootp 0xa0000000 u-boot.bin; " \
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"then " \
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"protect off 0x0 0x3ffff; " \
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"erase 0x0 0x3ffff; " \
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"cp.b 0xa0000000 0x0 0x40000; " \
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"reset; " \
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"fi\0" \
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"prog_uzImage_net=" \
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"mw.b 0xa0000000 0xff 0x100000; " \
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"if bootp 0xa0000000 uzImage; " \
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"then " \
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"protect off 0x40000 0xfffff; " \
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"erase 0x40000 0xfffff; " \
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"cp.b 0xa0000000 0x40000 0x100000; " \
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"fi\0" \
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"prog_jffs_net=" \
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"mw.b 0xa0000000 0xff 0x1e00000; " \
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"if bootp 0xa0000000 root.jffs; " \
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"then " \
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"protect off 0x140000 0x1f3ffff; " \
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"erase 0x140000 0x1f3ffff; " \
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"cp.b 0xa0000000 0x140000 0x1e00000; " \
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"fi\0"
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/* "erase_env=" */
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/* "protect off" */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
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#else
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#endif
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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#define RTC 1 /* enable 32KHz osc */
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#ifdef CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_PXA_MMC_GENERIC
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#define CONFIG_CMD_MMC
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#define CONFIG_SYS_MMC_BASE 0xF0000000
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
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#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
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#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000
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#define CONFIG_SYS_DRAM_SIZE 0x04000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
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#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
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#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
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#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
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#define CONFIG_SYS_GAFR2_U_VAL 0x2
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#define CONFIG_SYS_GPCR0_VAL 0x1800400
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#define CONFIG_SYS_GPCR1_VAL 0x0
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#define CONFIG_SYS_GPCR2_VAL 0x0
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#define CONFIG_SYS_GPDR0_VAL 0xc1818440
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#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
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#define CONFIG_SYS_GPDR2_VAL 0x1ffff
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#define CONFIG_SYS_GPSR0_VAL 0x8000
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#define CONFIG_SYS_GPSR1_VAL 0x3f0002
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#define CONFIG_SYS_GPSR2_VAL 0x1c000
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#define CONFIG_SYS_PSSR_VAL 0x20
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#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
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#define CONFIG_SYS_CKEN 0x0
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/*
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* Memory settings
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*/
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#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2
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#define CONFIG_SYS_MSC1_VAL 0x43AC494C
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#define CONFIG_SYS_MSC2_VAL 0x39D449D4
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#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
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#define CONFIG_SYS_MDREFR_VAL 0x0085C017
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#define CONFIG_SYS_MDMRS_VAL 0x00220022
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#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
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#define CONFIG_SYS_SXCNFG_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CONFIG_SYS_MECR_VAL 0x00000003
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#define CONFIG_SYS_MCMEM0_VAL 0x00014405
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#define CONFIG_SYS_MCMEM1_VAL 0x00014405
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#define CONFIG_SYS_MCATT0_VAL 0x00014405
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#define CONFIG_SYS_MCATT1_VAL 0x00014405
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#define CONFIG_SYS_MCIO0_VAL 0x00014405
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#define CONFIG_SYS_MCIO1_VAL 0x00014405
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/*
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_MONITOR_BASE 0
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#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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/* put cfg at end of flash for now */
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#define CONFIG_ENV_IS_IN_FLASH 1
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/* Addr of Environment Sector */
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
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#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
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#define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
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#endif /* __CONFIG_H */
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