mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
3fa66db459
Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
492 lines
16 KiB
C
492 lines
16 KiB
C
/*
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* (C) Copyright 2013 Keymile AG
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* Valentin Longchamp <valentin.longchamp@keymile.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CONFIG_KMP204X_H
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#define _CONFIG_KMP204X_H
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#define CONFIG_PHYS_64BIT
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#define CONFIG_PPC_P2041
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#define CONFIG_SYS_TEXT_BASE 0xfff40000
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#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
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/* an additionnal option is required for UBI as subpage access is
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* supported in u-boot */
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#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
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#define CONFIG_NAND_ECC_BCH
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_DISPLAY_BOARDINFO
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/* common KM defines */
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#include "keymile-common.h"
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_RAMBOOT_PBL
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
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#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
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/* High Level Configuration Options */
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#define CONFIG_BOOKE
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#define CONFIG_E500 /* BOOKE e500 family */
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#define CONFIG_E500MC /* BOOKE e500mc family */
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#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_MP /* support multiple processors */
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_PCI /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 /* PCIE controler 1 */
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#define CONFIG_PCIE3 /* PCIE controler 3 */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_SYS_DPAA_RMAN /* RMan */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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/* Environment in SPI Flash */
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 20000000
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#define CONFIG_ENV_SPI_MODE 0
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */
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#define CONFIG_ENV_SIZE 0x004000 /* 16K env */
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#define CONFIG_ENV_SECT_SIZE 0x010000
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#define CONFIG_ENV_OFFSET_REDUND 0x110000
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#define CONFIG_ENV_TOTAL_SIZE 0x020000
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#ifndef __ASSEMBLY__
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unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_SYS_CACHE_STASHING
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#define CONFIG_BACKSIDE_L2_CACHE
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#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_ADDR_MAP
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#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
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#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
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#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
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CONFIG_RAMBOOT_TEXT_BASE)
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#define CONFIG_SYS_L3_SIZE (1024 << 10)
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#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
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#define CONFIG_SYS_DCSRBAR 0xf0000000
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#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
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/*
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* DDR Setup
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*/
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_FSL_DDR3
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#define CONFIG_FSL_DDR_INTERACTIVE
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS 0x54
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#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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/******************************************************************************
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* (PRAM usage)
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* ... -------------------------------------------------------
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* ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
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* ... |<------------------- pram -------------------------->|
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* ... -------------------------------------------------------
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* @END_OF_RAM:
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* @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
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* @CONFIG_KM_PHRAM: address for /var
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* @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
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* @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
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*/
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/* size of rootfs in RAM */
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#define CONFIG_KM_ROOTFSSIZE 0x0
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/* pseudo-non volatile RAM [hex] */
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#define CONFIG_KM_PNVRAM 0x80000
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/* physical RAM MTD size [hex] */
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#define CONFIG_KM_PHRAM 0x100000
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/* reserved pram area at the end of memory [hex]
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* u-boot reserves some memory for the MP boot page */
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#define CONFIG_KM_RESERVED_PRAM 0x1000
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/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
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* is not valid yet, which is the case for when u-boot copies itself to RAM */
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#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
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#define CONFIG_KM_CRAMFS_ADDR 0x2000000
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#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
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#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
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/*
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* Local Bus Definitions
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*/
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/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
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#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
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/* Nand Flash */
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_SYS_NAND_BASE 0xffa00000
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#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_BCH
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/* NAND flash config */
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#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
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| OR_FCM_BCTLD /* LBCTL not ass */ \
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| OR_FCM_SCY_1 /* 1 clk wait cycle */ \
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| OR_FCM_RST /* 1 clk read setup */ \
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| OR_FCM_PGS /* Large page size */ \
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| OR_FCM_CST) /* 0.25 command setup */
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#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
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/* QRIO FPGA */
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#define CONFIG_SYS_QRIO_BASE 0xfb000000
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#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
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#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
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| BR_PS_8 /* Port Size 8 bits */ \
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| BR_DECC_OFF /* no error corr */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
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| OR_GPCM_BCTLD /* no LCTL assert */ \
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| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
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| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
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| OR_GPCM_TRLX /* relaxed tmgs */ \
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| OR_GPCM_EAD) /* extra bus clk cycles */
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#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
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/* bootcounter in QRIO */
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#define CONFIG_BOOTCOUNT_LIMIT
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#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
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#define CONFIG_MISC_INIT_F
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#define CONFIG_MISC_INIT_R
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#define CONFIG_LAST_STAGE_INIT
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#define CONFIG_HWCONFIG
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/* define to use L1 as initial stack */
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#define CONFIG_L1_INIT_RAM
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
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#define CONFIG_KM_CONSOLE_TTY "ttyS0"
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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/* new uImage format support */
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#define CONFIG_FIT
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#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_INIT_BOARD
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#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
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#define CONFIG_SYS_NUM_I2C_BUSES 3
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#define CONFIG_SYS_I2C_MAX_HOPS 1
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#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
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}
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#ifndef __ASSEMBLY__
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void set_sda(int state);
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void set_scl(int state);
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int get_sda(void);
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int get_scl(void);
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#endif
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#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_FSL_ESPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#define CONFIG_SF_DEFAULT_MODE 0
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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/* controller 3, Slot 1, tgtid 1, Base address 202000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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/* Qman/Bman */
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#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
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#define CONFIG_SYS_BMAN_NUM_PORTALS 10
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#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
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#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
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#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
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#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
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#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
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CONFIG_SYS_BMAN_CENA_SIZE)
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#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
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#define CONFIG_SYS_QMAN_NUM_PORTALS 10
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#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
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#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
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#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
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#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
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#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
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CONFIG_SYS_QMAN_CENA_SIZE)
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#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
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#define CONFIG_SYS_DPAA_FMAN
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#define CONFIG_SYS_DPAA_PME
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/* Default address of microcode for the Linux Fman driver
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* env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
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* ucode is stored after env, so we got 0x120000.
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*/
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#define CONFIG_SYS_QE_FW_IN_SPIFLASH
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#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
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#define CONFIG_FMAN_ENET
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#define CONFIG_PHYLIB_10G
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#define CONFIG_PHY_MARVELL /* there is a marvell phy */
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_E1000
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_DOS_PARTITION
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/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
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#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
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#define CONFIG_SYS_TBIPA_VALUE 8
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#define CONFIG_PHYLIB /* recommended PHY management */
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#define CONFIG_ETHPRIME "FM1@DTSEC5"
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#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
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/*
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* Environment
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*/
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* Hardware Watchdog
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*/
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#define CONFIG_WATCHDOG /* enable CPU watchdog */
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#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
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#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
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/*
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* additionnal command line configuration.
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*/
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_ERRATA
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/* we don't need flash support */
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#define CONFIG_SYS_NO_FLASH
|
|
#undef CONFIG_CMD_IMLS
|
|
#undef CONFIG_CMD_FLASH
|
|
#undef CONFIG_FLASH_CFI_MTD
|
|
#undef CONFIG_JFFS2_CMDLINE
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 64 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
|
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
|
|
|
#ifdef CONFIG_CMD_KGDB
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
|
#endif
|
|
|
|
#define __USB_PHY_TYPE utmi
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
#define CONFIG_ENV_OVERWRITE
|
|
#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
|
|
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
|
|
#endif
|
|
|
|
#ifndef MTDIDS_DEFAULT
|
|
# define MTDIDS_DEFAULT "nand0=fsl_elbc_nand"
|
|
#endif /* MTDIDS_DEFAULT */
|
|
|
|
#ifndef MTDPARTS_DEFAULT
|
|
# define MTDPARTS_DEFAULT "mtdparts=" \
|
|
"fsl_elbc_nand:" \
|
|
"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
|
|
#endif /* MTDPARTS_DEFAULT */
|
|
|
|
/* architecture specific default bootargs */
|
|
#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
|
|
|
|
/* FIXME: FDT_ADDR is unspecified */
|
|
#define CONFIG_KM_DEF_ENV_CPU \
|
|
"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
|
|
"cramfsloadfdt=" \
|
|
"cramfsload ${fdt_addr_r} " \
|
|
"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
|
|
"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
|
|
"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \
|
|
"update=" \
|
|
"sf probe 0;sf erase 0 +${filesize};" \
|
|
"sf write ${load_addr_r} 0 ${filesize};\0" \
|
|
"set_fdthigh=true\0" \
|
|
""
|
|
|
|
#define CONFIG_HW_ENV_SETTINGS \
|
|
"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
|
|
"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
|
|
"usb_dr_mode=host\0"
|
|
|
|
#define CONFIG_KM_NEW_ENV \
|
|
"newenv=sf probe 0;" \
|
|
"sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
|
|
__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
|
|
|
|
/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
|
|
#ifndef CONFIG_KM_DEF_ARCH
|
|
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
|
|
#endif
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
CONFIG_KM_DEF_ENV \
|
|
CONFIG_KM_DEF_ARCH \
|
|
CONFIG_KM_NEW_ENV \
|
|
CONFIG_HW_ENV_SETTINGS \
|
|
"EEprom_ivm=pca9547:70:9\0" \
|
|
""
|
|
|
|
#endif /* _CONFIG_KMP204X_H */
|