mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
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*/
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#ifndef __GXBB_H__
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#define __GXBB_H__
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#define GXBB_FIRMWARE_MEM_SIZE 0x1000000
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#define GXBB_AOBUS_BASE 0xc8100000
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#define GXBB_PERIPHS_BASE 0xc8834400
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#define GXBB_HIU_BASE 0xc883c000
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#define GXBB_ETH_BASE 0xc9410000
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/* Always-On Peripherals registers */
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#define GXBB_AO_ADDR(off) (GXBB_AOBUS_BASE + ((off) << 2))
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#define GXBB_AO_SEC_GP_CFG0 GXBB_AO_ADDR(0x90)
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#define GXBB_AO_SEC_GP_CFG3 GXBB_AO_ADDR(0x93)
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#define GXBB_AO_SEC_GP_CFG4 GXBB_AO_ADDR(0x94)
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#define GXBB_AO_SEC_GP_CFG5 GXBB_AO_ADDR(0x95)
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#define GXBB_AO_MEM_SIZE_MASK 0xFFFF0000
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#define GXBB_AO_MEM_SIZE_SHIFT 16
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#define GXBB_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
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#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16
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#define GXBB_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
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/* Peripherals registers */
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#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
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/* GPIO registers 0 to 6 */
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#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
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#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
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#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
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#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
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#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
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#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
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#define GXBB_ETH_REG_2 GXBB_PERIPHS_ADDR(0x56)
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#define GXBB_ETH_REG_3 GXBB_PERIPHS_ADDR(0x57)
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#define GXBB_ETH_REG_0_PHY_INTF BIT(0)
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#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define GXBB_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define GXBB_ETH_REG_0_CLK_EN BIT(12)
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/* HIU registers */
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#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2))
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#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40)
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/* Ethernet memory power domain */
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#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
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/* Clock gates */
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#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50)
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#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51)
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#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52)
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#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53)
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#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54)
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#define GXBB_GCLK_MPEG_0_I2C BIT(9)
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#define GXBB_GCLK_MPEG_1_ETH BIT(3)
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#endif /* __GXBB_H__ */
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