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Update PPLL to 676MHz and PMU_PCLK to 48MHz, because: 1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz can not, 2. We think 48MHz is fast enough for pmu pclk and it is lower power cost than 99MHz, 3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using internally for kernel,it suppose not to change the bus clock like pmu_pclk in kernel, so we want to change it in uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
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.. | ||
clock.h | ||
cru_rk3036.h | ||
cru_rk3288.h | ||
cru_rk3399.h | ||
ddr_rk3288.h | ||
edp_rk3288.h | ||
gpio.h | ||
grf_rk3036.h | ||
grf_rk3288.h | ||
grf_rk3399.h | ||
hardware.h | ||
hdmi_rk3288.h | ||
i2c.h | ||
lvds_rk3288.h | ||
periph.h | ||
pmu_rk3288.h | ||
pwm.h | ||
sdram.h | ||
sdram_rk3036.h | ||
sys_proto.h | ||
timer.h | ||
uart.h | ||
vop_rk3288.h |