u-boot/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
Stefan Roese 4adb46a314 arm: armada-xp: Fix SPL for AXP by using save_boot_params_ret
Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced
a different method to return from save_boot_params(). The SPL support
for AXP has been pulled and changing to this new method is now
required for SPL to work correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-04-11 11:49:00 +02:00

61 lines
1.1 KiB
ArmAsm

/*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
b save_boot_params_ret
ENDPROC(save_boot_params)
/*
* cache_inv - invalidate Cache line
* r0 - dest
*/
.global cache_inv
.type cache_inv, %function
cache_inv:
stmfd sp!, {r1-r12}
mcr p15, 0, r0, c7, c6, 1
ldmfd sp!, {r1-r12}
bx lr
/*
* flush_l1_v6 - l1 cache clean invalidate
* r0 - dest
*/
.global flush_l1_v6
.type flush_l1_v6, %function
flush_l1_v6:
stmfd sp!, {r1-r12}
mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
ldmfd sp!, {r1-r12}
bx lr
/*
* flush_l1_v7 - l1 cache clean invalidate
* r0 - dest
*/
.global flush_l1_v7
.type flush_l1_v7, %function
flush_l1_v7:
stmfd sp!, {r1-r12}
dmb /* @data memory barrier */
mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
dsb /* @data sync barrier */
ldmfd sp!, {r1-r12}
bx lr