mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 07:13:03 +00:00
67bd6158d4
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct make to generate kwbimage with NAND header. This image is used for booting from NAND flash (either SPI or parallel). Support is very simple, SPL after finishes DDR training returns back to the BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and executes U-Boot proper. To generate correct kwbimage NAND header, it is required to set following Kconfig options: CONFIG_SYS_NAND_PAGE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION They are used only by make / mkimage when generating final kwbimage. CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig option which is set into kwbimage NAND_BADBLK_LOCATION header field. Signed-off-by: Pali Rohár <pali@kernel.org>
791 lines
23 KiB
Text
791 lines
23 KiB
Text
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menuconfig MTD_RAW_NAND
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bool "Raw NAND Device Support"
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if MTD_RAW_NAND
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config SYS_NAND_SELF_INIT
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bool
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help
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This option, if enabled, provides more flexible and linux-like
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NAND initialization process.
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config SPL_SYS_NAND_SELF_INIT
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bool
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depends on !SPL_NAND_SIMPLE
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help
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This option, if enabled, provides more flexible and linux-like
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NAND initialization process, in SPL.
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config TPL_SYS_NAND_SELF_INIT
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bool
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depends on TPL_NAND_SUPPORT
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help
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This option, if enabled, provides more flexible and linux-like
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NAND initialization process, in SPL.
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config TPL_NAND_INIT
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bool
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config SPL_NAND_INIT
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bool
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config SYS_MAX_NAND_DEVICE
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int "Maximum number of NAND devices to support"
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default 1
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config SYS_NAND_DRIVER_ECC_LAYOUT
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bool "Omit standard ECC layouts to save space"
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help
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Omit standard ECC layouts to save space. Select this if your driver
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is known to provide its own ECC layout.
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config SYS_NAND_USE_FLASH_BBT
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bool "Enable BBT (Bad Block Table) support"
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help
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Enable the BBT (Bad Block Table) usage.
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config SYS_NAND_NO_SUBPAGE_WRITE
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bool "Disable subpage write support"
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depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD
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config DM_NAND_ATMEL
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bool "Support Atmel NAND controller with DM support"
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select SYS_NAND_SELF_INIT
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imply SYS_NAND_USE_FLASH_BBT
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help
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Enable this driver for NAND flash platforms using an Atmel NAND
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controller.
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config NAND_ATMEL
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bool "Support Atmel NAND controller"
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select SYS_NAND_SELF_INIT
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imply SYS_NAND_USE_FLASH_BBT
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help
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Enable this driver for NAND flash platforms using an Atmel NAND
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controller.
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if NAND_ATMEL
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config ATMEL_NAND_HWECC
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bool "Atmel Hardware ECC"
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config ATMEL_NAND_HW_PMECC
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bool "Atmel Programmable Multibit ECC (PMECC)"
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select ATMEL_NAND_HWECC
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help
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The Programmable Multibit ECC (PMECC) controller is a programmable
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binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
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config PMECC_CAP
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int "PMECC Correctable ECC Bits"
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depends on ATMEL_NAND_HW_PMECC
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default 2
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help
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Correctable ECC bits, can be 2, 4, 8, 12, and 24.
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config PMECC_SECTOR_SIZE
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int "PMECC Sector Size"
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depends on ATMEL_NAND_HW_PMECC
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default 512
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help
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Sector size, in bytes, can be 512 or 1024.
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config SPL_GENERATE_ATMEL_PMECC_HEADER
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bool "Atmel PMECC Header Generation"
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depends on SPL
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select ATMEL_NAND_HWECC
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select ATMEL_NAND_HW_PMECC
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help
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Generate Programmable Multibit ECC (PMECC) header for SPL image.
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choice
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prompt "NAND bus width (bits)"
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default SYS_NAND_DBW_8
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config SYS_NAND_DBW_8
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bool "NAND bus width is 8 bits"
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config SYS_NAND_DBW_16
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bool "NAND bus width is 16 bits"
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endchoice
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endif
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config NAND_BRCMNAND
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bool "Support Broadcom NAND controller"
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depends on OF_CONTROL && DM && DM_MTD
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select SYS_NAND_SELF_INIT
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help
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Enable the driver for NAND flash on platforms using a Broadcom NAND
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controller.
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config NAND_BRCMNAND_6368
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bool "Support Broadcom NAND controller on bcm6368"
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depends on NAND_BRCMNAND && ARCH_BMIPS
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help
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Enable support for broadcom nand driver on bcm6368.
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config NAND_BRCMNAND_6753
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bool "Support Broadcom NAND controller on bcm6753"
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depends on NAND_BRCMNAND && BCM6855
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help
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Enable support for broadcom nand driver on bcm6753.
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config NAND_BRCMNAND_68360
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bool "Support Broadcom NAND controller on bcm68360"
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depends on NAND_BRCMNAND && BCM6856
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help
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Enable support for broadcom nand driver on bcm68360.
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config NAND_BRCMNAND_6838
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bool "Support Broadcom NAND controller on bcm6838"
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depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
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help
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Enable support for broadcom nand driver on bcm6838.
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config NAND_BRCMNAND_6858
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bool "Support Broadcom NAND controller on bcm6858"
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depends on NAND_BRCMNAND && BCM6858
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help
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Enable support for broadcom nand driver on bcm6858.
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config NAND_BRCMNAND_63158
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bool "Support Broadcom NAND controller on bcm63158"
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depends on NAND_BRCMNAND && BCM63158
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help
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Enable support for broadcom nand driver on bcm63158.
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config NAND_DAVINCI
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bool "Support TI Davinci NAND controller"
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select SYS_NAND_SELF_INIT if TARGET_DA850EVM
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help
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Enable this driver for NAND flash controllers available in TI Davinci
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and Keystone2 platforms
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choice
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prompt "Type of ECC used on NAND"
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default SYS_NAND_4BIT_HW_ECC_OOBFIRST
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depends on NAND_DAVINCI
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config SYS_NAND_HW_ECC
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bool "Use 1-bit HW ECC"
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config SYS_NAND_4BIT_HW_ECC_OOBFIRST
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bool "Use 4-bit HW ECC with OOB at the front"
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config SYS_NAND_SOFT_ECC
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bool "Use software ECC"
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endchoice
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choice
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prompt "NAND page size"
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depends on NAND_DAVINCI
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default SYS_NAND_PAGE_2K
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config SYS_NAND_PAGE_2K
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bool "Page size is 2K"
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config SYS_NAND_PAGE_4K
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bool "Page size is 4K"
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endchoice
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config KEYSTONE_RBL_NAND
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depends on ARCH_KEYSTONE
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def_bool y
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config SPL_NAND_LOAD
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def_bool y
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depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
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config NAND_DENALI
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bool
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select SYS_NAND_SELF_INIT
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imply CMD_NAND
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config NAND_DENALI_DT
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bool "Support Denali NAND controller as a DT device"
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select NAND_DENALI
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select SPL_SYS_NAND_SELF_INIT
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depends on OF_CONTROL && DM_MTD
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help
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Enable the driver for NAND flash on platforms using a Denali NAND
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controller as a DT device.
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config NAND_FSL_ELBC
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bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
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select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
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select SPL_SYS_NAND_SELF_INIT
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select SYS_NAND_SELF_INIT
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depends on FSL_ELBC
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help
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Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
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config NAND_FSL_ELBC_DT
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bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
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depends on NAND_FSL_ELBC
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config NAND_FSL_IFC
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bool "Support Freescale Integrated Flash Controller NAND driver"
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select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
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select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
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select SPL_SYS_NAND_SELF_INIT
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select SYS_NAND_SELF_INIT
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select FSL_IFC
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help
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Enable the Freescale Integrated Flash Controller NAND driver.
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config NAND_KIRKWOOD
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bool "Support for Kirkwood NAND controller"
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depends on ARCH_KIRKWOOD
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default y
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config NAND_ECC_BCH
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bool
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config NAND_KMETER1
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bool "Support KMETER1 NAND controller"
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depends on VENDOR_KM
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select NAND_ECC_BCH
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config NAND_LPC32XX_MLC
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bool "Support LPC32XX_MLC controller"
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select SYS_NAND_SELF_INIT
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help
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Enable the LPC32XX MLC NAND controller.
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config NAND_LPC32XX_SLC
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bool "Support LPC32XX_SLC controller"
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help
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Enable the LPC32XX SLC NAND controller.
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config NAND_OMAP_GPMC
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bool "Support OMAP GPMC NAND controller"
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depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
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select SYS_NAND_SELF_INIT if ARCH_K3
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select SPL_NAND_INIT if ARCH_K3
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select SPL_SYS_NAND_SELF_INIT if ARCH_K3
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help
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Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
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GPMC controller is used for parallel NAND flash devices, and can
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do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
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and BCH16 ECC algorithms.
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if NAND_OMAP_GPMC
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config NAND_OMAP_GPMC_PREFETCH
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bool "Enable GPMC Prefetch"
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default y
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help
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On OMAP platforms that use the GPMC controller
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(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
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uses the prefetch mode to speed up read operations.
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config NAND_OMAP_ELM
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bool "Enable ELM driver for OMAPxx and AMxx platforms."
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depends on !OMAP34XX
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help
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ELM controller is used for ECC error detection (not ECC calculation)
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of BCH4, BCH8 and BCH16 ECC algorithms.
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Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
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thus such SoC platforms need to depend on software library for ECC error
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detection. However ECC calculation on such plaforms would still be
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done by GPMC controller.
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choice
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prompt "ECC scheme"
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default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
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help
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On OMAP platforms, this CONFIG specifies NAND ECC scheme.
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It can take following values:
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OMAP_ECC_HAM1_CODE_SW
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1-bit Hamming code using software lib.
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(for legacy devices only)
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OMAP_ECC_HAM1_CODE_HW
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1-bit Hamming code using GPMC hardware.
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(for legacy devices only)
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
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4-bit BCH code (unsupported)
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OMAP_ECC_BCH4_CODE_HW
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4-bit BCH code (unsupported)
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
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8-bit BCH code with
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- ecc calculation using GPMC hardware engine,
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- error detection using software library.
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- requires CONFIG_BCH to enable software BCH library
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(For legacy device which do not have ELM h/w engine)
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OMAP_ECC_BCH8_CODE_HW
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8-bit BCH code with
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- ecc calculation using GPMC hardware engine,
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- error detection using ELM hardware engine.
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OMAP_ECC_BCH16_CODE_HW
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16-bit BCH code with
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- ecc calculation using GPMC hardware engine,
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- error detection using ELM hardware engine.
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How to select ECC scheme on OMAP and AMxx platforms ?
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-----------------------------------------------------
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Though higher ECC schemes have more capability to detect and correct
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bit-flips, but still selection of ECC scheme is dependent on following
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- hardware engines present in SoC.
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Some legacy OMAP SoC do not have ELM h/w engine thus such
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SoC cannot support BCHx_HW ECC schemes.
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- size of OOB/Spare region
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With higher ECC schemes, more OOB/Spare area is required to
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store ECC. So choice of ECC scheme is limited by NAND oobsize.
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In general following expression can help:
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NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
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where
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NAND_OOBSIZE = number of bytes available in
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OOB/spare area per NAND page.
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NAND_PAGESIZE = bytes in main-area of NAND page.
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ECC_BYTES = number of ECC bytes generated to
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protect 512 bytes of data, which is:
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3 for HAM1_xx ecc schemes
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7 for BCH4_xx ecc schemes
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14 for BCH8_xx ecc schemes
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26 for BCH16_xx ecc schemes
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example to check for BCH16 on 2K page NAND
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NAND_PAGESIZE = 2048
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NAND_OOBSIZE = 64
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2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
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Thus BCH16 cannot be supported on 2K page NAND.
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However, for 4K pagesize NAND
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NAND_PAGESIZE = 4096
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NAND_OOBSIZE = 224
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ECC_BYTES = 26
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2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
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Thus BCH16 can be supported on 4K page NAND.
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config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
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bool "1-bit Hamming code using software lib"
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config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
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bool "1-bit Hamming code using GPMC hardware"
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config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
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bool "8-bit BCH code with HW calculation SW error detection"
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config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
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bool "8-bit BCH code with HW calculation and error detection"
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config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
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bool "16-bit BCH code with HW calculation and error detection"
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endchoice
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config NAND_OMAP_ECCSCHEME
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int
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default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
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default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
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default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
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default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
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default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
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help
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This must be kept in sync with the enum in
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include/linux/mtd/omap_gpmc.h
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endif
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config NAND_VF610_NFC
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bool "Support for Freescale NFC for VF610"
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select SYS_NAND_SELF_INIT
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select SYS_NAND_DRIVER_ECC_LAYOUT
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imply CMD_NAND
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help
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Enables support for NAND Flash Controller on some Freescale
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processors like the VF610, MCF54418 or Kinetis K70.
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The driver supports a maximum 2k page size. The driver
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currently does not support hardware ECC.
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if NAND_VF610_NFC
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config NAND_VF610_NFC_DT
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bool "Support Vybrid's vf610 NAND controller as a DT device"
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depends on OF_CONTROL && DM_MTD
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help
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Enable the driver for Vybrid's vf610 NAND flash on platforms
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using device tree.
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choice
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prompt "Hardware ECC strength"
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depends on NAND_VF610_NFC
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default SYS_NAND_VF610_NFC_45_ECC_BYTES
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help
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Select the ECC strength used in the hardware BCH ECC block.
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config SYS_NAND_VF610_NFC_45_ECC_BYTES
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bool "24-error correction (45 ECC bytes)"
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config SYS_NAND_VF610_NFC_60_ECC_BYTES
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bool "32-error correction (60 ECC bytes)"
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endchoice
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endif
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config NAND_PXA3XX
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bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
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select SYS_NAND_SELF_INIT
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select DM_MTD
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select REGMAP
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select SYSCON
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imply CMD_NAND
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help
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This enables the driver for the NAND flash device found on
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PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
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config NAND_SUNXI
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bool "Support for NAND on Allwinner SoCs"
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default ARCH_SUNXI
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depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
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select SYS_NAND_SELF_INIT
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select SYS_NAND_U_BOOT_LOCATIONS
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select SPL_NAND_SUPPORT
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select SPL_SYS_NAND_SELF_INIT
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imply CMD_NAND
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---help---
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Enable support for NAND. This option enables the standard and
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SPL drivers.
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The SPL driver only supports reading from the NAND using DMA
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transfers.
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if NAND_SUNXI
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config NAND_SUNXI_SPL_ECC_STRENGTH
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int "Allwinner NAND SPL ECC Strength"
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default 64
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config NAND_SUNXI_SPL_ECC_SIZE
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int "Allwinner NAND SPL ECC Step Size"
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default 1024
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config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
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int "Allwinner NAND SPL Usable Page Size"
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default 1024
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endif
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config NAND_ARASAN
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bool "Configure Arasan Nand"
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select SYS_NAND_SELF_INIT
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depends on DM_MTD
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imply CMD_NAND
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help
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This enables Nand driver support for Arasan nand flash
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controller. This uses the hardware ECC for read and
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write operations.
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config NAND_MXC
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bool "MXC NAND support"
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depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
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imply CMD_NAND
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help
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This enables the NAND driver for the NAND flash controller on the
|
|
i.MX27 / i.MX31 / i.MX5 processors.
|
|
|
|
config SYS_NAND_SIZE
|
|
int "Size of NAND in kilobytes"
|
|
depends on NAND_MXC && SPL_NAND_SUPPORT
|
|
default 268435456
|
|
|
|
config MXC_NAND_HWECC
|
|
bool "Hardware ECC support in MXC NAND"
|
|
depends on NAND_MXC
|
|
|
|
config NAND_MXS
|
|
bool "MXS NAND support"
|
|
depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
|
|
select SPL_SYS_NAND_SELF_INIT
|
|
select SYS_NAND_SELF_INIT
|
|
imply CMD_NAND
|
|
select APBH_DMA
|
|
select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
|
|
select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
|
|
help
|
|
This enables NAND driver for the NAND flash controller on the
|
|
MXS processors.
|
|
|
|
if NAND_MXS
|
|
|
|
config NAND_MXS_DT
|
|
bool "Support MXS NAND controller as a DT device"
|
|
depends on OF_CONTROL && DM_MTD
|
|
help
|
|
Enable the driver for MXS NAND flash on platforms using
|
|
device tree.
|
|
|
|
config NAND_MXS_USE_MINIMUM_ECC
|
|
bool "Use minimum ECC strength supported by the controller"
|
|
default false
|
|
|
|
endif
|
|
|
|
config NAND_MXIC
|
|
bool "Macronix raw NAND controller"
|
|
select SYS_NAND_SELF_INIT
|
|
help
|
|
This selects the Macronix raw NAND controller driver.
|
|
|
|
config NAND_ZYNQ
|
|
bool "Support for Zynq Nand controller"
|
|
select SPL_SYS_NAND_SELF_INIT
|
|
select SYS_NAND_SELF_INIT
|
|
select DM_MTD
|
|
imply CMD_NAND
|
|
help
|
|
This enables Nand driver support for Nand flash controller
|
|
found on Zynq SoC.
|
|
|
|
config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
|
|
bool "Enable use of 1st stage bootloader timing for NAND"
|
|
depends on NAND_ZYNQ
|
|
help
|
|
This flag prevent U-boot reconfigure NAND flash controller and reuse
|
|
the NAND timing from 1st stage bootloader.
|
|
|
|
config NAND_OCTEONTX
|
|
bool "Support for OcteonTX NAND controller"
|
|
select SYS_NAND_SELF_INIT
|
|
imply CMD_NAND
|
|
help
|
|
This enables Nand flash controller hardware found on the OcteonTX
|
|
processors.
|
|
|
|
config NAND_OCTEONTX_HW_ECC
|
|
bool "Support Hardware ECC for OcteonTX NAND controller"
|
|
depends on NAND_OCTEONTX
|
|
default y
|
|
help
|
|
This enables Hardware BCH engine found on the OcteonTX processors to
|
|
support ECC for NAND flash controller.
|
|
|
|
config NAND_STM32_FMC2
|
|
bool "Support for NAND controller on STM32MP SoCs"
|
|
depends on ARCH_STM32MP
|
|
select SYS_NAND_SELF_INIT
|
|
imply CMD_NAND
|
|
help
|
|
Enables support for NAND Flash chips on SoCs containing the FMC2
|
|
NAND controller. This controller is found on STM32MP SoCs.
|
|
The controller supports a maximum 8k page size and supports
|
|
a maximum 8-bit correction error per sector of 512 bytes.
|
|
|
|
config CORTINA_NAND
|
|
bool "Support for NAND controller on Cortina-Access SoCs"
|
|
depends on CORTINA_PLATFORM
|
|
select SYS_NAND_SELF_INIT
|
|
select DM_MTD
|
|
imply CMD_NAND
|
|
help
|
|
Enables support for NAND Flash chips on Coartina-Access SoCs platform
|
|
This controller is found on Presidio/Venus SoCs.
|
|
The controller supports a maximum 8k page size and supports
|
|
a maximum 40-bit error correction per sector of 1024 bytes.
|
|
|
|
config ROCKCHIP_NAND
|
|
bool "Support for NAND controller on Rockchip SoCs"
|
|
depends on ARCH_ROCKCHIP
|
|
select SYS_NAND_SELF_INIT
|
|
select DM_MTD
|
|
imply CMD_NAND
|
|
help
|
|
Enables support for NAND Flash chips on Rockchip SoCs platform.
|
|
This controller is found on Rockchip SoCs.
|
|
There are four different versions of NAND FLASH Controllers,
|
|
including:
|
|
NFC v600: RK2928, RK3066, RK3188
|
|
NFC v622: RK3036, RK3128
|
|
NFC v800: RK3308, RV1108
|
|
NFC v900: PX30, RK3326
|
|
|
|
config TEGRA_NAND
|
|
bool "Support for NAND controller on Tegra SoCs"
|
|
depends on ARCH_TEGRA
|
|
select SYS_NAND_SELF_INIT
|
|
imply CMD_NAND
|
|
help
|
|
Enables support for NAND Flash chips on Tegra SoCs platforms.
|
|
|
|
config NAND_MT7621
|
|
bool "Support for MediaTek MT7621 NAND flash controller"
|
|
depends on SOC_MT7621
|
|
select SYS_NAND_SELF_INIT
|
|
select SPL_SYS_NAND_SELF_INIT
|
|
imply CMD_NAND
|
|
help
|
|
This enables NAND driver for the NAND flash controller on MediaTek
|
|
MT7621 platform.
|
|
The controller supports 4~12 bits correction per 512 bytes with a
|
|
maximum 4KB page size.
|
|
|
|
comment "Generic NAND options"
|
|
|
|
config SYS_NAND_BLOCK_SIZE
|
|
hex "NAND chip eraseblock size"
|
|
depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT || \
|
|
MVEBU_SPL_BOOT_DEVICE_NAND
|
|
depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
|
|
!NAND_FSL_IFC && !NAND_MT7621
|
|
help
|
|
Number of data bytes in one eraseblock for the NAND chip on the
|
|
board. This is the multiple of NAND_PAGE_SIZE and the number of
|
|
pages.
|
|
|
|
config SYS_NAND_ONFI_DETECTION
|
|
bool "Enable detection of ONFI compliant devices during probe"
|
|
help
|
|
Enables detection of ONFI compliant devices during probe.
|
|
And fetching device parameters flashed on device, by parsing
|
|
ONFI parameter page.
|
|
|
|
config SYS_NAND_PAGE_COUNT
|
|
hex "NAND chip page count"
|
|
depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
|
|
SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \
|
|
NAND_OMAP_GPMC)
|
|
help
|
|
Number of pages in the NAND chip.
|
|
|
|
config SYS_NAND_PAGE_SIZE
|
|
hex "NAND chip page size"
|
|
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
|
|
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
|
|
MVEBU_SPL_BOOT_DEVICE_NAND || \
|
|
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
|
|
depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
|
|
help
|
|
Number of data bytes in one page for the NAND chip on the
|
|
board, not including the OOB area.
|
|
|
|
config SYS_NAND_OOBSIZE
|
|
hex "NAND chip OOB size"
|
|
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
|
|
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
|
|
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
|
|
depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
|
|
help
|
|
Number of bytes in the Out-Of-Band area for the NAND chip on
|
|
the board.
|
|
|
|
# Enhance depends when converting drivers to Kconfig which use this config
|
|
# option (mxc_nand, ndfc, omap_gpmc).
|
|
config SYS_NAND_BUSWIDTH_16BIT
|
|
bool "Use 16-bit NAND interface"
|
|
depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
|
|
help
|
|
Indicates that NAND device has 16-bit wide data-bus. In absence of this
|
|
config, bus-width of NAND device is assumed to be either 8-bit and later
|
|
determined by reading ONFI params.
|
|
Above config is useful when NAND device's bus-width information cannot
|
|
be determined from on-chip ONFI params, like in following scenarios:
|
|
- SPL boot does not support reading of ONFI parameters. This is done to
|
|
keep SPL code foot-print small.
|
|
- In current U-Boot flow using nand_init(), driver initialization
|
|
happens in board_nand_init() which is called before any device probe
|
|
(nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
|
|
not available while configuring controller. So a static CONFIG_NAND_xx
|
|
is needed to know the device's bus-width in advance.
|
|
|
|
if SPL
|
|
|
|
config SYS_NAND_5_ADDR_CYCLE
|
|
bool "Wait 5 address cycles during NAND commands"
|
|
depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
|
|
(SPL_NAND_SUPPORT && NAND_ATMEL)
|
|
default y
|
|
help
|
|
Some controllers require waiting for 5 address cycles when issuing
|
|
some commands, on NAND chips larger than 128MiB.
|
|
|
|
choice
|
|
prompt "NAND bad block marker/indicator position in the OOB"
|
|
depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
|
|
SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
|
|
default HAS_NAND_LARGE_BADBLOCK_POS
|
|
help
|
|
In the OOB, which position contains the badblock information.
|
|
|
|
config HAS_NAND_LARGE_BADBLOCK_POS
|
|
bool "Set the bad block marker/indicator to the 'large' position"
|
|
|
|
config HAS_NAND_SMALL_BADBLOCK_POS
|
|
bool "Set the bad block marker/indicator to the 'small' position"
|
|
|
|
endchoice
|
|
|
|
config SYS_NAND_BAD_BLOCK_POS
|
|
int
|
|
default 0 if HAS_NAND_LARGE_BADBLOCK_POS
|
|
default 5 if HAS_NAND_SMALL_BADBLOCK_POS
|
|
|
|
config SYS_NAND_U_BOOT_LOCATIONS
|
|
bool "Define U-boot binaries locations in NAND"
|
|
help
|
|
Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
|
|
This option should not be enabled when compiling U-boot for boards
|
|
defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
|
|
file.
|
|
|
|
config SYS_NAND_U_BOOT_OFFS
|
|
hex "Location in NAND to read U-Boot from"
|
|
default 0x800000 if NAND_SUNXI
|
|
depends on SYS_NAND_U_BOOT_LOCATIONS
|
|
help
|
|
Set the offset from the start of the nand where u-boot should be
|
|
loaded from.
|
|
|
|
config SYS_NAND_U_BOOT_OFFS_REDUND
|
|
hex "Location in NAND to read U-Boot from"
|
|
default SYS_NAND_U_BOOT_OFFS
|
|
depends on SYS_NAND_U_BOOT_LOCATIONS
|
|
help
|
|
Set the offset from the start of the nand where the redundant u-boot
|
|
should be loaded from.
|
|
|
|
config SPL_NAND_AM33XX_BCH
|
|
bool "Enables SPL-NAND driver which supports ELM based"
|
|
depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
|
|
default y
|
|
help
|
|
Hardware ECC correction. This is useful for platforms which have ELM
|
|
hardware engine and use NAND boot mode.
|
|
Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
|
|
so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
|
|
SPL-NAND driver with software ECC correction support.
|
|
|
|
config SPL_NAND_DENALI
|
|
bool "Support Denali NAND controller for SPL"
|
|
depends on SPL_NAND_SUPPORT
|
|
help
|
|
This is a small implementation of the Denali NAND controller
|
|
for use on SPL.
|
|
|
|
config NAND_DENALI_SPARE_AREA_SKIP_BYTES
|
|
int "Number of bytes skipped in OOB area"
|
|
depends on SPL_NAND_DENALI
|
|
range 0 63
|
|
help
|
|
This option specifies the number of bytes to skip from the beginning
|
|
of OOB area before last ECC sector data starts. This is potentially
|
|
used to preserve the bad block marker in the OOB area.
|
|
|
|
config SPL_NAND_SIMPLE
|
|
bool "Use simple SPL NAND driver"
|
|
depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
|
|
help
|
|
Support for NAND boot using simple NAND drivers that
|
|
expose the cmd_ctrl() interface.
|
|
|
|
config SYS_NAND_HW_ECC_OOBFIRST
|
|
bool "In SPL, read the OOB first and then the data from NAND"
|
|
depends on SPL_NAND_SIMPLE
|
|
|
|
endif
|
|
|
|
endif # if NAND
|