mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 22:33:18 +00:00
401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
253 lines
6.6 KiB
C
253 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <env.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/bitops.h>
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#include <linux/libfdt.h>
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#include <altera.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <watchdog.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/nic301.h>
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#include <asm/arch/scu.h>
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#include <asm/pl310.h>
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#include <dt-bindings/reset/altr,rst-mgr.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static struct nic301_registers *nic301_regs =
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(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
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static struct scu_registers *scu_regs =
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(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
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/*
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* FPGA programming support for SoC FPGA Cyclone V
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*/
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static Altera_desc altera_fpga[] = {
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{
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/* Family */
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Altera_SoCFPGA,
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/* Interface type */
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fast_passive_parallel,
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/* No limitation as additional data will be ignored */
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-1,
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/* No device function table */
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NULL,
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/* Base interface address specified in driver */
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NULL,
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/* No cookie implementation */
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0
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},
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};
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static const struct {
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const u16 pn;
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const char *name;
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const char *var;
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} socfpga_fpga_model[] = {
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/* Cyclone V E */
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{ 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
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{ 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
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{ 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
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{ 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
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{ 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
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/* Cyclone V GX/GT */
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{ 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
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{ 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
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{ 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
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{ 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
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{ 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
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/* Cyclone V SE/SX/ST */
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{ 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
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{ 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
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{ 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
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{ 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
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/* Arria V */
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{ 0x2d03, "Arria V, D5", "av_d5" },
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/* Arria V ST/SX */
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{ 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" },
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};
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static int socfpga_fpga_id(const bool print_id)
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{
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const u32 altera_mi = 0x6e;
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const u32 id = scan_mgr_get_fpga_id();
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const u32 lsb = id & 0x00000001;
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const u32 mi = (id >> 1) & 0x000007ff;
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const u32 pn = (id >> 12) & 0x0000ffff;
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const u32 version = (id >> 28) & 0x0000000f;
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int i;
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if ((mi != altera_mi) || (lsb != 1)) {
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printf("FPGA: Not Altera chip ID\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
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if (pn == socfpga_fpga_model[i].pn)
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break;
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if (i == ARRAY_SIZE(socfpga_fpga_model)) {
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printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id);
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return -EINVAL;
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}
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if (print_id)
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printf("FPGA: Altera %s, version 0x%01x\n",
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socfpga_fpga_model[i].name, version);
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return i;
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}
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/*
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* Print CPU information
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*/
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
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SYSMGR_GEN5_BOOTINFO);
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const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
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puts("CPU: Altera SoCFPGA Platform\n");
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socfpga_fpga_id(1);
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printf("BOOT: %s\n", bsel_str[bsel].name);
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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const u32 bsel = readl(socfpga_get_sysmgr_addr() +
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SYSMGR_GEN5_BOOTINFO) & 0x7;
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const int fpga_id = socfpga_fpga_id(0);
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env_set("bootmode", bsel_str[bsel].mode);
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if (fpga_id >= 0)
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env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
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return 0;
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}
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#endif
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/*
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* Convert all NIC-301 AMBA slaves from secure to non-secure
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*/
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static void socfpga_nic301_slave_ns(void)
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{
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writel(0x1, &nic301_regs->lwhps2fpgaregs);
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writel(0x1, &nic301_regs->hps2fpgaregs);
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writel(0x1, &nic301_regs->acp);
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writel(0x1, &nic301_regs->rom);
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writel(0x1, &nic301_regs->ocram);
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writel(0x1, &nic301_regs->sdrdata);
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}
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void socfpga_sdram_remap_zero(void)
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{
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u32 remap;
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socfpga_nic301_slave_ns();
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/*
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* Private components security:
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* U-Boot : configure private timer, global timer and cpu component
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* access as non secure for kernel stage (as required by Linux)
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*/
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setbits_le32(&scu_regs->sacr, 0xfff);
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/* Configure the L2 controller to make SDRAM start at 0 */
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remap = 0x1; /* remap.mpuzero */
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/* Keep fpga bridge enabled when running from FPGA onchip RAM */
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if (socfpga_is_booting_from_fpga())
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remap |= 0x8; /* remap.hps2fpga */
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writel(remap, &nic301_regs->remap);
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writel(0x1, &pl310->pl310_addr_filter_start);
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}
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static u32 iswgrp_handoff[8];
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int arch_early_init_r(void)
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{
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int i;
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/*
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* Write magic value into magic register to unlock support for
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* issuing warm reset. The ancient kernel code expects this
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* value to be written into the register by the bootloader, so
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* to support that old code, we write it here instead of in the
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* reset_cpu() function just before resetting the CPU.
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*/
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writel(0xae9efebc,
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socfpga_get_sysmgr_addr() + SYSMGR_GEN5_WARMRAMGRP_EN);
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for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
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iswgrp_handoff[i] = readl(socfpga_get_sysmgr_addr() +
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SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
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socfpga_bridges_reset(1);
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socfpga_sdram_remap_zero();
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/* Add device descriptor to FPGA device table */
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socfpga_fpga_add(&altera_fpga[0]);
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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static struct socfpga_sdr_ctrl *sdr_ctrl =
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(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
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void do_bridge_reset(int enable, unsigned int mask)
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{
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int i;
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if (enable) {
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socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
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!(mask & BIT(1)),
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!(mask & BIT(2)));
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for (i = 0; i < 2; i++) { /* Reload SW setting cache */
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iswgrp_handoff[i] =
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readl(socfpga_get_sysmgr_addr() +
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SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
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}
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writel(iswgrp_handoff[2],
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socfpga_get_sysmgr_addr() +
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SYSMGR_GEN5_FPGAINFGRP_MODULE);
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writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
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writel(iswgrp_handoff[0],
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socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
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writel(iswgrp_handoff[1], &nic301_regs->remap);
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writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
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writel(iswgrp_handoff[0],
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socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
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} else {
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writel(0, socfpga_get_sysmgr_addr() +
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SYSMGR_GEN5_FPGAINFGRP_MODULE);
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writel(0, &sdr_ctrl->fpgaport_rst);
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writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
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writel(1, &nic301_regs->remap);
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}
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}
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#endif
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