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https://github.com/AsahiLinux/u-boot
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63f832fbb8
The framebuffer driver for MX5 is based on CONFIG_LCD. In the current implementation, there is a serious bug because the required memory is allocated before relocation, but the driver knows only later which is the resolution of the display. The patch switches the driver to CONFIG_VIDEO and the memory is allocated by the driver itself. We also need to switch the vision2 board code and config file in the same commit so that this commit will be bisectable. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Anatolij Gustschin <agust@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
219 lines
5.4 KiB
C
219 lines
5.4 KiB
C
/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the MX51-3Stack Freescale board.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MX51 /* in a mx51 */
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#define CONFIG_SYS_TEXT_BASE 0x97800000
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_MX5_HCLK 24000000
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#define CONFIG_SYS_MX5_CLK32 32768
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_REVISION_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define BOARD_LATE_INIT
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#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_SYS_MX51_UART3
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#define CONFIG_MXC_GPIO
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#define CONFIG_MXC_SPI
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#define CONFIG_HW_WATCHDOG
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/*
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* SPI Configs
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* */
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#define CONFIG_FSL_SF
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#define CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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/*
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* Use gpio 4 pin 25 as chip select for SPI flash
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* This corresponds to gpio 121
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*/
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#define CONFIG_SPI_FLASH_CS (1 | (121 << 8))
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 25000000
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#define CONFIG_ENV_SPI_CS (1 | (121 << 8))
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_MAX_HZ 25000000
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#define CONFIG_ENV_SPI_MODE SPI_MODE_0
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
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#define CONFIG_ENV_SIZE (4 * 1024)
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#define CONFIG_FSL_ENV_IN_SF
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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/* PMIC Controller */
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 0
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 2500000
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#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
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#define CONFIG_RTC_MC13783
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/*
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* MMC Configs
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*/
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#define CONFIG_FSL_ESDHC
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#ifdef CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
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#define CONFIG_SYS_FSL_ESDHC_NUM 1
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#define CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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#endif
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#define CONFIG_CMD_DATE
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/*
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* Eth Configs
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*/
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#define CONFIG_HAS_ETH1
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#define CONFIG_MII
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#define CONFIG_DISCOVER_PHY
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1F
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
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/***********************************************************
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* Command definition
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***********************************************************/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_SPI
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#undef CONFIG_CMD_IMLS
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"loadaddr=0x90800000\0"
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "Vision II U-boot > "
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x90000000
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#define CONFIG_SYS_MEMTEST_END 0x10000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "Vision II U-boot > "
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/*
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* Stack sizes
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*/
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#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
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#define PHYS_SDRAM_2 CSD1_BASE_ADDR
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#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE 0x90000000
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#define CONFIG_SYS_INIT_RAM_ADDR 0x1FFE8000
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#define CONFIG_SYS_INIT_RAM_SIZE (64 * 1024)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_GBL_DATA_OFFSET)
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#define CONFIG_BOARD_EARLY_INIT_F
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/* 166 MHz DDR RAM */
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#define CONFIG_SYS_DDR_CLKSEL 0
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#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
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#define CONFIG_SYS_NO_FLASH
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/*
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* Framebuffer and LCD
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*/
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#define CONFIG_PREBOOT
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_MX5
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_CMD_BMP
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#define CONFIG_BMP_16BPP
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#endif /* __CONFIG_H */
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