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https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
319 lines
7.8 KiB
C
319 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale i.MX28 I2C Driver
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Partly based on Linux kernel i2c-mxs.c driver:
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* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
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*
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* Which was based on a (non-working) driver which was:
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#include <common.h>
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#include <malloc.h>
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#include <i2c.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MXS_I2C_MAX_TIMEOUT 1000000
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static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
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{
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if (adap->hwadapnr == 0)
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return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
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else
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return (struct mxs_i2c_regs *)MXS_I2C1_BASE;
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}
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static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
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{
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
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uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
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uint32_t timing0;
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timing0 = readl(&i2c_regs->hw_i2c_timing0);
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/*
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* This is a reverse version of the algorithm presented in
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* i2c_set_bus_speed(). Please refer there for details.
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*/
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return clk / ((((timing0 >> 16) - 3) * 2) + 38);
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}
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static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
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{
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
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/*
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* The timing derivation algorithm. There is no documentation for this
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* algorithm available, it was derived by using the scope and fiddling
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* with constants until the result observed on the scope was good enough
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* for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
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* possible to assume the algorithm works for other frequencies as well.
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*
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* Note it was necessary to cap the frequency on both ends as it's not
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* possible to configure completely arbitrary frequency for the I2C bus
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* clock.
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*/
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uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
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uint32_t base = ((clk / speed) - 38) / 2;
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uint16_t high_count = base + 3;
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uint16_t low_count = base - 3;
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uint16_t rcv_count = (high_count * 3) / 4;
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uint16_t xmit_count = low_count / 4;
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if (speed > 540000) {
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printf("MXS I2C: Speed too high (%d Hz)\n", speed);
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return -EINVAL;
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}
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if (speed < 12000) {
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printf("MXS I2C: Speed too low (%d Hz)\n", speed);
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return -EINVAL;
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}
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writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
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writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
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writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
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(0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
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&i2c_regs->hw_i2c_timing2);
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return 0;
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}
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static void mxs_i2c_reset(struct i2c_adapter *adap)
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{
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
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int ret;
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int speed = mxs_i2c_get_bus_speed(adap);
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ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
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if (ret) {
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debug("MXS I2C: Block reset timeout\n");
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return;
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}
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writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
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I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
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I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
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&i2c_regs->hw_i2c_ctrl1_clr);
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writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
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mxs_i2c_set_bus_speed(adap, speed);
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}
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static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
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{
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
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writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
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I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
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(1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
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&i2c_regs->hw_i2c_queuecmd);
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writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
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writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
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(len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
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I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
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writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
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}
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static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buf, int blen, int stop)
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{
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
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uint32_t data, tmp;
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int i, remain, off;
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int timeout = MXS_I2C_MAX_TIMEOUT;
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if ((alen > 4) || (alen == 0)) {
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debug("MXS I2C: Invalid address length\n");
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return -EINVAL;
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}
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if (stop)
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stop = I2C_QUEUECMD_POST_SEND_STOP;
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writel(I2C_QUEUECMD_PRE_SEND_START |
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I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
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((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
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&i2c_regs->hw_i2c_queuecmd);
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data = (chip << 1) << 24;
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for (i = 0; i < alen; i++) {
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data >>= 8;
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data |= ((char *)&addr)[alen - i - 1] << 24;
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if ((i & 3) == 2)
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writel(data, &i2c_regs->hw_i2c_data);
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}
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off = i;
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for (; i < off + blen; i++) {
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data >>= 8;
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data |= buf[i - off] << 24;
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if ((i & 3) == 2)
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writel(data, &i2c_regs->hw_i2c_data);
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}
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remain = 24 - ((i & 3) * 8);
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if (remain)
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writel(data >> remain, &i2c_regs->hw_i2c_data);
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writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
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while (--timeout) {
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tmp = readl(&i2c_regs->hw_i2c_queuestat);
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if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
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break;
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}
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if (!timeout) {
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debug("MXS I2C: Failed transmitting data!\n");
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return -EINVAL;
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}
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return 0;
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}
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static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
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{
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
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uint32_t tmp;
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int timeout = MXS_I2C_MAX_TIMEOUT;
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for (;;) {
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tmp = readl(&i2c_regs->hw_i2c_ctrl1);
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if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
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debug("MXS I2C: No slave ACK\n");
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goto err;
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}
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if (tmp & (
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I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
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I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
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debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
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goto err;
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}
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if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
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break;
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if (!timeout--) {
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debug("MXS I2C: Operation timed out\n");
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goto err;
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}
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udelay(1);
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}
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return 0;
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err:
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mxs_i2c_reset(adap);
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return 1;
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}
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static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
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uint addr, int alen, uint8_t *buffer,
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int len)
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{
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
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uint32_t tmp = 0;
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int timeout = MXS_I2C_MAX_TIMEOUT;
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int ret;
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int i;
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ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
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if (ret) {
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debug("MXS I2C: Failed writing address\n");
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return ret;
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}
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ret = mxs_i2c_wait_for_ack(adap);
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if (ret) {
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debug("MXS I2C: Failed writing address\n");
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return ret;
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}
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mxs_i2c_setup_read(adap, chip, len);
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ret = mxs_i2c_wait_for_ack(adap);
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if (ret) {
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debug("MXS I2C: Failed reading address\n");
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return ret;
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}
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for (i = 0; i < len; i++) {
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if (!(i & 3)) {
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while (--timeout) {
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tmp = readl(&i2c_regs->hw_i2c_queuestat);
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if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
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break;
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}
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if (!timeout) {
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debug("MXS I2C: Failed receiving data!\n");
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return -ETIMEDOUT;
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}
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tmp = readl(&i2c_regs->hw_i2c_queuedata);
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}
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buffer[i] = tmp & 0xff;
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tmp >>= 8;
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}
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return 0;
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}
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static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
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uint addr, int alen, uint8_t *buffer,
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int len)
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{
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int ret;
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ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
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if (ret) {
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debug("MXS I2C: Failed writing address\n");
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return ret;
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}
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ret = mxs_i2c_wait_for_ack(adap);
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if (ret)
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debug("MXS I2C: Failed writing address\n");
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return ret;
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}
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static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
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{
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int ret;
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ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
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if (!ret)
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ret = mxs_i2c_wait_for_ack(adap);
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mxs_i2c_reset(adap);
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return ret;
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}
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static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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mxs_i2c_reset(adap);
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mxs_i2c_set_bus_speed(adap, speed);
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return;
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}
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U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
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mxs_i2c_if_read, mxs_i2c_if_write,
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mxs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, 0, 0)
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U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe,
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mxs_i2c_if_read, mxs_i2c_if_write,
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mxs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, 0, 1)
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