mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
73c38934da
When the CPU is in non-secure (NS) mode (when running U-Boot under a
secure monitor), certain actions cannot be taken, since they would need
to write to secure-only registers. One example is configuring the ARM
architectural timer's CNTFRQ register.
We could support this in one of two ways:
1) Compile twice, once for secure mode (in which case anything goes) and
once for non-secure mode (in which case certain actions are disabled).
This complicates things, since everyone needs to keep track of
different U-Boot binaries for different situations.
2) Detect NS mode at run-time, and optionally skip any impossible actions.
This has the advantage of a single U-Boot binary working in all cases.
(2) is not possible on ARM in general, since there's no architectural way
to detect secure-vs-non-secure. However, there is a Tegra-specific way to
detect this.
This patches uses that feature to detect secure vs. NS mode on Tegra, and
uses that to:
* Skip the ARM arch timer initialization.
* Set/clear an environment variable so that boot scripts can take
different action depending on which mode the CPU is in. This might be
something like:
if CPU is secure:
load secure monitor code into RAM.
boot secure monitor.
secure monitor will restart (a new copy of) U-Boot in NS mode.
else:
execute normal boot process
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
80 lines
2 KiB
C
80 lines
2 KiB
C
/*
|
|
* (C) Copyright 2010-2011
|
|
* NVIDIA Corporation <www.nvidia.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
#include <asm/types.h>
|
|
|
|
/* Stabilization delays, in usec */
|
|
#define PLL_STABILIZATION_DELAY (300)
|
|
#define IO_STABILIZATION_DELAY (1000)
|
|
|
|
#define PLLX_ENABLED (1 << 30)
|
|
#define CCLK_BURST_POLICY 0x20008888
|
|
#define SUPER_CCLK_DIVIDER 0x80000000
|
|
|
|
/* Calculate clock fractional divider value from ref and target frequencies */
|
|
#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
|
|
|
|
/* Calculate clock frequency value from reference and clock divider value */
|
|
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
|
|
|
|
/* AVP/CPU ID */
|
|
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
|
|
#define PG_UP_TAG_0 0x0
|
|
|
|
#define CORESIGHT_UNLOCK 0xC5ACCE55;
|
|
|
|
/* AP base physical address of internal SRAM */
|
|
#define NV_PA_BASE_SRAM 0x40000000
|
|
|
|
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
|
|
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
|
|
#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
|
|
|
|
#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
|
|
#define FLOW_MODE_STOP 2
|
|
#define HALT_COP_EVENT_JTAG (1 << 28)
|
|
#define HALT_COP_EVENT_IRQ_1 (1 << 11)
|
|
#define HALT_COP_EVENT_FIQ_1 (1 << 9)
|
|
|
|
/* This is the main entry into U-Boot, used by the Cortex-A9 */
|
|
extern void _start(void);
|
|
|
|
/**
|
|
* Works out the SOC/SKU type used for clocks settings
|
|
*
|
|
* @return SOC type - see TEGRA_SOC...
|
|
*/
|
|
int tegra_get_chip_sku(void);
|
|
|
|
/**
|
|
* Returns the pure SOC (chip ID) from the HIDREV register
|
|
*
|
|
* @return SOC ID - see CHIPID_TEGRAxx...
|
|
*/
|
|
int tegra_get_chip(void);
|
|
|
|
/**
|
|
* Returns the SKU ID from the sku_info register
|
|
*
|
|
* @return SKU ID - see SKU_ID_Txx...
|
|
*/
|
|
int tegra_get_sku_info(void);
|
|
|
|
/* Do any chip-specific cache config */
|
|
void config_cache(void);
|
|
|
|
#if defined(CONFIG_TEGRA124)
|
|
/* Do chip-specific vpr config */
|
|
void config_vpr(void);
|
|
#else
|
|
static inline void config_vpr(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
|
|
bool tegra_cpu_is_non_secure(void);
|
|
#endif
|