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https://github.com/AsahiLinux/u-boot
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ee0a846246
Remove individual CPU specific DSPI driver. Add required feature for the common DSPI driver in cpu_init and in platform configuration file. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
158 lines
5.2 KiB
C
158 lines
5.2 KiB
C
/*
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* MCF5227x Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __DSPI_H__
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#define __DSPI_H__
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/* DMA Serial Peripheral Interface (DSPI) */
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typedef struct dspi {
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u32 mcr; /* 0x00 */
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u32 resv0; /* 0x04 */
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u32 tcr; /* 0x08 */
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u32 ctar[8]; /* 0x0C - 0x28 */
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u32 sr; /* 0x2C */
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u32 irsr; /* 0x30 */
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u32 tfr; /* 0x34 - PUSHR */
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u16 resv1; /* 0x38 */
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u16 rfr; /* 0x3A - POPR */
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#ifdef CONFIG_MCF547x_8x
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u32 tfdr[4]; /* 0x3C */
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u8 resv2[0x30]; /* 0x40 */
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u32 rfdr[4]; /* 0x7C */
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#else
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u32 tfdr[16]; /* 0x3C */
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u32 rfdr[16]; /* 0x7C */
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#endif
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} dspi_t;
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/* Module configuration */
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#define DSPI_MCR_MSTR (0x80000000)
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#define DSPI_MCR_CSCK (0x40000000)
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#define DSPI_MCR_DCONF(x) (((x)&0x03)<<28)
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#define DSPI_MCR_FRZ (0x08000000)
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#define DSPI_MCR_MTFE (0x04000000)
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#define DSPI_MCR_PCSSE (0x02000000)
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#define DSPI_MCR_ROOE (0x01000000)
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#define DSPI_MCR_CSIS7 (0x00800000)
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#define DSPI_MCR_CSIS6 (0x00400000)
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#define DSPI_MCR_CSIS5 (0x00200000)
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#define DSPI_MCR_CSIS4 (0x00100000)
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#define DSPI_MCR_CSIS3 (0x00080000)
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#define DSPI_MCR_CSIS2 (0x00040000)
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#define DSPI_MCR_CSIS1 (0x00020000)
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#define DSPI_MCR_CSIS0 (0x00010000)
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#define DSPI_MCR_MDIS (0x00004000)
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#define DSPI_MCR_DTXF (0x00002000)
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#define DSPI_MCR_DRXF (0x00001000)
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#define DSPI_MCR_CTXF (0x00000800)
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#define DSPI_MCR_CRXF (0x00000400)
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#define DSPI_MCR_SMPL_PT(x) (((x)&0x03)<<8)
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#define DSPI_MCR_HALT (0x00000001)
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/* Transfer count */
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#define DSPI_TCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
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/* Clock and transfer attributes */
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#define DSPI_CTAR_DBR (0x80000000)
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#define DSPI_CTAR_TRSZ(x) (((x)&0x0F)<<27)
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#define DSPI_CTAR_CPOL (0x04000000)
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#define DSPI_CTAR_CPHA (0x02000000)
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#define DSPI_CTAR_LSBFE (0x01000000)
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#define DSPI_CTAR_PCSSCK(x) (((x)&0x03)<<22)
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#define DSPI_CTAR_PCSSCK_7CLK (0x00A00000)
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#define DSPI_CTAR_PCSSCK_5CLK (0x00800000)
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#define DSPI_CTAR_PCSSCK_3CLK (0x00400000)
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#define DSPI_CTAR_PCSSCK_1CLK (0x00000000)
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#define DSPI_CTAR_PASC(x) (((x)&0x03)<<20)
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#define DSPI_CTAR_PASC_7CLK (0x00300000)
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#define DSPI_CTAR_PASC_5CLK (0x00200000)
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#define DSPI_CTAR_PASC_3CLK (0x00100000)
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#define DSPI_CTAR_PASC_1CLK (0x00000000)
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#define DSPI_CTAR_PDT(x) (((x)&0x03)<<18)
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#define DSPI_CTAR_PDT_7CLK (0x000A0000)
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#define DSPI_CTAR_PDT_5CLK (0x00080000)
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#define DSPI_CTAR_PDT_3CLK (0x00040000)
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#define DSPI_CTAR_PDT_1CLK (0x00000000)
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#define DSPI_CTAR_PBR(x) (((x)&0x03)<<16)
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#define DSPI_CTAR_PBR_7CLK (0x00030000)
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#define DSPI_CTAR_PBR_5CLK (0x00020000)
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#define DSPI_CTAR_PBR_3CLK (0x00010000)
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#define DSPI_CTAR_PBR_1CLK (0x00000000)
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#define DSPI_CTAR_CSSCK(x) (((x)&0x0F)<<12)
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#define DSPI_CTAR_ASC(x) (((x)&0x0F)<<8)
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#define DSPI_CTAR_DT(x) (((x)&0x0F)<<4)
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#define DSPI_CTAR_BR(x) (((x)&0x0F))
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/* Status */
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#define DSPI_SR_TCF (0x80000000)
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#define DSPI_SR_TXRXS (0x40000000)
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#define DSPI_SR_EOQF (0x10000000)
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#define DSPI_SR_TFUF (0x08000000)
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#define DSPI_SR_TFFF (0x02000000)
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#define DSPI_SR_RFOF (0x00080000)
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#define DSPI_SR_RFDF (0x00020000)
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#define DSPI_SR_TXCTR(x) (((x)&0x0F)<<12)
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#define DSPI_SR_TXPTR(x) (((x)&0x0F)<<8)
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#define DSPI_SR_RXCTR(x) (((x)&0x0F)<<4)
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#define DSPI_SR_RXPTR(x) (((x)&0x0F))
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/* DMA/interrupt request selct and enable */
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#define DSPI_IRSR_TCFE (0x80000000)
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#define DSPI_IRSR_EOQFE (0x10000000)
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#define DSPI_IRSR_TFUFE (0x08000000)
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#define DSPI_IRSR_TFFFE (0x02000000)
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#define DSPI_IRSR_TFFFS (0x01000000)
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#define DSPI_IRSR_RFOFE (0x00080000)
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#define DSPI_IRSR_RFDFE (0x00020000)
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#define DSPI_IRSR_RFDFS (0x00010000)
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/* Transfer control - 32-bit access */
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#define DSPI_TFR_CONT (0x80000000)
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#define DSPI_TFR_CTAS(x) (((x)&0x07)<<12)
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#define DSPI_TFR_EOQ (0x08000000)
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#define DSPI_TFR_CTCNT (0x04000000)
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#define DSPI_TFR_CS7 (0x00800000)
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#define DSPI_TFR_CS6 (0x00400000)
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#define DSPI_TFR_CS5 (0x00200000)
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#define DSPI_TFR_CS4 (0x00100000)
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#define DSPI_TFR_CS3 (0x00080000)
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#define DSPI_TFR_CS2 (0x00040000)
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#define DSPI_TFR_CS1 (0x00020000)
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#define DSPI_TFR_CS0 (0x00010000)
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/* Transfer Fifo */
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#define DSPI_TFR_TXDATA(x) (((x)&0xFFFF))
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/* Bit definitions and macros for DRFR */
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#define DSPI_RFR_RXDATA(x) (((x)&0xFFFF))
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/* Bit definitions and macros for DTFDR group */
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#define DSPI_TFDR_TXDATA(x) (((x)&0x0000FFFF))
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#define DSPI_TFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for DRFDR group */
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#define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF))
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#endif /* __DSPI_H__ */
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