mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
9925f1dbc3
In order that we can use eth_env_* even when CONFIG_NET isn't set, move
these functions to environment code from net code.
This fixes failures such as:
board/ti/am335x/built-in.o: In function `board_late_init':
board/ti/am335x/board.c:752: undefined reference to `eth_env_set_enetaddr'
u-boot/board/ti/am335x/board.c:766: undefined reference to `eth_env_set_enetaddr'
which caters for use cases such as:
commit f411b5cca4 ("board: am335x: Always set eth/eth1addr environment
variable")
when Ethernet is required in Linux, but not U-Boot.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
249 lines
5.8 KiB
C
249 lines
5.8 KiB
C
/*
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* board/renesas/koelsch/koelsch.c
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#include <common.h>
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#include <malloc.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <environment.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/sh_sdhi.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <div64.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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u32 stc;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* CPU frequency setting. Set to 1.5GHz */
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stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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/* QoS */
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qos_init();
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}
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#define TMU0_MSTP125 (1 << 25)
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#define SCIF0_MSTP721 (1 << 21)
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#define ETHER_MSTP813 (1 << 13)
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#define SDHI0_MSTP314 (1 << 14)
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#define SDHI1_MSTP312 (1 << 12)
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#define SDHI2_MSTP311 (1 << 11)
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#define SD1CKCR 0xE6150078
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#define SD2CKCR 0xE615026C
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#define SD_97500KHZ 0x7
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int board_early_init_f(void)
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{
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/* SCIF0 */
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
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/* ETHER */
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
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/* SDHI */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
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SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
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/*
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* SD0 clock is set to 97.5MHz by default.
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* Set SD1 and SD2 to the 97.5MHz as well.
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*/
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writel(SD_97500KHZ, SD1CKCR);
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writel(SD_97500KHZ, SD2CKCR);
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return 0;
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}
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/* LSI pin pull-up control */
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#define PUPR5 0xe6060114
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#define PUPR5_ETH 0x3FFC0000
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#define PUPR5_ETH_MAGIC (1 << 27)
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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/* Init PFC controller */
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r8a7791_pinmux_init();
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/* ETHER Enable */
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gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
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gpio_request(GPIO_FN_ETH_RX_ER, NULL);
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gpio_request(GPIO_FN_ETH_RXD0, NULL);
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gpio_request(GPIO_FN_ETH_RXD1, NULL);
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gpio_request(GPIO_FN_ETH_LINK, NULL);
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gpio_request(GPIO_FN_ETH_REFCLK, NULL);
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gpio_request(GPIO_FN_ETH_MDIO, NULL);
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gpio_request(GPIO_FN_ETH_TXD1, NULL);
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gpio_request(GPIO_FN_ETH_TX_EN, NULL);
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gpio_request(GPIO_FN_ETH_TXD0, NULL);
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gpio_request(GPIO_FN_ETH_MDC, NULL);
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gpio_request(GPIO_FN_IRQ0, NULL);
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
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gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
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gpio_direction_output(GPIO_GP_5_22, 0);
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mdelay(20);
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gpio_set_value(GPIO_GP_5_22, 1);
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udelay(1);
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return 0;
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}
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#define CXR24 0xEE7003C0 /* MAC address high register */
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#define CXR25 0xEE7003C8 /* MAC address low register */
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SH_ETHER
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int ret = -ENODEV;
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u32 val;
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unsigned char enetaddr[6];
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ret = sh_eth_initialize(bis);
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if (!eth_env_get_enetaddr("ethaddr", enetaddr))
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return ret;
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/* Set Mac address */
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val = enetaddr[0] << 24 | enetaddr[1] << 16 |
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enetaddr[2] << 8 | enetaddr[3];
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writel(val, CXR24);
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val = enetaddr[4] << 8 | enetaddr[5];
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writel(val, CXR25);
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return ret;
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#else
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return 0;
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#endif
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret = -ENODEV;
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#ifdef CONFIG_SH_SDHI
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gpio_request(GPIO_FN_SD0_DATA0, NULL);
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gpio_request(GPIO_FN_SD0_DATA1, NULL);
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gpio_request(GPIO_FN_SD0_DATA2, NULL);
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gpio_request(GPIO_FN_SD0_DATA3, NULL);
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gpio_request(GPIO_FN_SD0_CLK, NULL);
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gpio_request(GPIO_FN_SD0_CMD, NULL);
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gpio_request(GPIO_FN_SD0_CD, NULL);
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gpio_request(GPIO_FN_SD2_DATA0, NULL);
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gpio_request(GPIO_FN_SD2_DATA1, NULL);
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gpio_request(GPIO_FN_SD2_DATA2, NULL);
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gpio_request(GPIO_FN_SD2_DATA3, NULL);
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gpio_request(GPIO_FN_SD2_CLK, NULL);
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gpio_request(GPIO_FN_SD2_CMD, NULL);
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gpio_request(GPIO_FN_SD2_CD, NULL);
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/* SDHI 0 */
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gpio_request(GPIO_GP_7_17, NULL);
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gpio_request(GPIO_GP_2_12, NULL);
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gpio_direction_output(GPIO_GP_7_17, 1); /* power on */
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gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
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SH_SDHI_QUIRK_16BIT_BUF);
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if (ret)
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return ret;
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/* SDHI 1 */
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gpio_request(GPIO_GP_7_18, NULL);
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gpio_request(GPIO_GP_2_13, NULL);
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gpio_direction_output(GPIO_GP_7_18, 1); /* power on */
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gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
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if (ret)
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return ret;
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/* SDHI 2 */
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gpio_request(GPIO_GP_7_19, NULL);
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gpio_request(GPIO_GP_2_26, NULL);
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gpio_direction_output(GPIO_GP_7_19, 1); /* power on */
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gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
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#endif
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return ret;
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}
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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/* koelsch has KSZ8041NL/RNL */
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#define PHY_CONTROL1 0x1E
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#define PHY_LED_MODE 0xC0000
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#define PHY_LED_MODE_ACK 0x4000
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int board_phy_config(struct phy_device *phydev)
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{
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int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
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ret &= ~PHY_LED_MODE;
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ret |= PHY_LED_MODE_ACK;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
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return 0;
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}
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const struct rmobile_sysinfo sysinfo = {
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CONFIG_ARCH_RMOBILE_BOARD_STRING
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};
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void reset_cpu(ulong addr)
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{
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u8 val;
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i2c_set_bus_num(2); /* PowerIC connected to ch2 */
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i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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val |= 0x02;
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i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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}
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static const struct sh_serial_platdata serial_platdata = {
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.base = SCIF0_BASE,
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.type = PORT_SCIF,
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.clk = 14745600,
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.clk_mode = EXT_CLK,
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};
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U_BOOT_DEVICE(koelsch_serials) = {
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.name = "serial_sh",
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.platdata = &serial_platdata,
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};
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