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ebb1a59325
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to release armada-18.09.2"). The complete log of changes is best obtained from the mv-ddr-marvell.git repository but some relevant highlights are: ddr3: add missing txsdll parameter ddr3: fix tfaw timimg parameter ddr3: fix trrd timimg parameter merge ddr3 topology header file with mv_ddr_topology one mv_ddr: a38x: fix zero memory size scrubbing issue The upstream code is incorporated omitting the portions not relevant to Armada-38x and DDR3. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \ -UA70X0 Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
375 lines
9.3 KiB
C
375 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#include "mv_ddr_spd.h"
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#define MV_DDR_SPD_DATA_MTB 125 /* medium timebase, ps */
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#define MV_DDR_SPD_DATA_FTB 1 /* fine timebase, ps */
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#define MV_DDR_SPD_MSB_OFFS 8 /* most significant byte offset, bits */
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#define MV_DDR_SPD_SUPPORTED_CLS_NUM 30
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static unsigned int mv_ddr_spd_supported_cls[MV_DDR_SPD_SUPPORTED_CLS_NUM];
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int mv_ddr_spd_supported_cls_calc(union mv_ddr_spd_data *spd_data)
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{
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unsigned int byte, bit, start_cl;
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start_cl = (spd_data->all_bytes[23] & 0x8) ? 23 : 7;
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for (byte = 20; byte < 23; byte++) {
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for (bit = 0; bit < 8; bit++) {
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if (spd_data->all_bytes[byte] & (1 << bit))
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mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = start_cl + (byte - 20) * 8 + bit;
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else
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mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = 0;
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}
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}
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for (byte = 23, bit = 0; bit < 6; bit++) {
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if (spd_data->all_bytes[byte] & (1 << bit))
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mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = start_cl + (byte - 20) * 8 + bit;
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else
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mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = 0;
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}
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return 0;
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}
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unsigned int mv_ddr_spd_supported_cl_get(unsigned int cl)
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{
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unsigned int supported_cl;
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int i = 0;
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while (i < MV_DDR_SPD_SUPPORTED_CLS_NUM &&
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mv_ddr_spd_supported_cls[i] < cl)
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i++;
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if (i < MV_DDR_SPD_SUPPORTED_CLS_NUM)
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supported_cl = mv_ddr_spd_supported_cls[i];
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else
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supported_cl = 0;
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return supported_cl;
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}
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int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[])
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{
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int calc_val;
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/* t ck avg min, ps */
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calc_val = spd_data->byte_fields.byte_18 * MV_DDR_SPD_DATA_MTB +
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(signed char)spd_data->byte_fields.byte_125 * MV_DDR_SPD_DATA_FTB;
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if (calc_val < 0)
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return 1;
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timing_data[MV_DDR_TCK_AVG_MIN] = calc_val;
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/* t aa min, ps */
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calc_val = spd_data->byte_fields.byte_24 * MV_DDR_SPD_DATA_MTB +
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(signed char)spd_data->byte_fields.byte_123 * MV_DDR_SPD_DATA_FTB;
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if (calc_val < 0)
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return 1;
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timing_data[MV_DDR_TAA_MIN] = calc_val;
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/* t rfc1 min, ps */
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timing_data[MV_DDR_TRFC1_MIN] = (spd_data->byte_fields.byte_30 +
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(spd_data->byte_fields.byte_31 << MV_DDR_SPD_MSB_OFFS)) * MV_DDR_SPD_DATA_MTB;
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/* t wr min, ps */
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timing_data[MV_DDR_TWR_MIN] = (spd_data->byte_fields.byte_42 +
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(spd_data->byte_fields.byte_41.bit_fields.t_wr_min_msn << MV_DDR_SPD_MSB_OFFS)) *
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MV_DDR_SPD_DATA_MTB;
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/* t rcd min, ps */
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calc_val = spd_data->byte_fields.byte_25 * MV_DDR_SPD_DATA_MTB +
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(signed char)spd_data->byte_fields.byte_122 * MV_DDR_SPD_DATA_FTB;
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if (calc_val < 0)
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return 1;
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timing_data[MV_DDR_TRCD_MIN] = calc_val;
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/* t rp min, ps */
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calc_val = spd_data->byte_fields.byte_26 * MV_DDR_SPD_DATA_MTB +
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(signed char)spd_data->byte_fields.byte_121 * MV_DDR_SPD_DATA_FTB;
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if (calc_val < 0)
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return 1;
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timing_data[MV_DDR_TRP_MIN] = calc_val;
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/* t rc min, ps */
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calc_val = (spd_data->byte_fields.byte_29 +
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(spd_data->byte_fields.byte_27.bit_fields.t_rc_min_msn << MV_DDR_SPD_MSB_OFFS)) *
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MV_DDR_SPD_DATA_MTB +
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(signed char)spd_data->byte_fields.byte_120 * MV_DDR_SPD_DATA_FTB;
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if (calc_val < 0)
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return 1;
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timing_data[MV_DDR_TRC_MIN] = calc_val;
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/* t ras min, ps */
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timing_data[MV_DDR_TRAS_MIN] = (spd_data->byte_fields.byte_28 +
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(spd_data->byte_fields.byte_27.bit_fields.t_ras_min_msn << MV_DDR_SPD_MSB_OFFS)) *
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MV_DDR_SPD_DATA_MTB;
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/* t rrd s min, ps */
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calc_val = spd_data->byte_fields.byte_38 * MV_DDR_SPD_DATA_MTB +
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(signed char)spd_data->byte_fields.byte_119 * MV_DDR_SPD_DATA_FTB;
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if (calc_val < 0)
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return 1;
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timing_data[MV_DDR_TRRD_S_MIN] = calc_val;
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/* t rrd l min, ps */
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calc_val = spd_data->byte_fields.byte_39 * MV_DDR_SPD_DATA_MTB +
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(signed char)spd_data->byte_fields.byte_118 * MV_DDR_SPD_DATA_FTB;
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if (calc_val < 0)
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return 1;
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timing_data[MV_DDR_TRRD_L_MIN] = calc_val;
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/* t ccd l min, ps */
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calc_val = spd_data->byte_fields.byte_40 * MV_DDR_SPD_DATA_MTB +
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(signed char)spd_data->byte_fields.byte_117 * MV_DDR_SPD_DATA_FTB;
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if (calc_val < 0)
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return 1;
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timing_data[MV_DDR_TCCD_L_MIN] = calc_val;
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/* t faw min, ps */
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timing_data[MV_DDR_TFAW_MIN] = (spd_data->byte_fields.byte_37 +
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(spd_data->byte_fields.byte_36.bit_fields.t_faw_min_msn << MV_DDR_SPD_MSB_OFFS)) *
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MV_DDR_SPD_DATA_MTB;
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/* t wtr s min, ps */
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timing_data[MV_DDR_TWTR_S_MIN] = (spd_data->byte_fields.byte_44 +
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(spd_data->byte_fields.byte_43.bit_fields.t_wtr_s_min_msn << MV_DDR_SPD_MSB_OFFS)) *
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MV_DDR_SPD_DATA_MTB;
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/* t wtr l min, ps */
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timing_data[MV_DDR_TWTR_L_MIN] = (spd_data->byte_fields.byte_45 +
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(spd_data->byte_fields.byte_43.bit_fields.t_wtr_l_min_msn << MV_DDR_SPD_MSB_OFFS)) *
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MV_DDR_SPD_DATA_MTB;
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return 0;
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}
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enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char dev_width = spd_data->byte_fields.byte_12.bit_fields.device_width;
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enum mv_ddr_dev_width ret_val;
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switch (dev_width) {
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case 0x00:
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ret_val = MV_DDR_DEV_WIDTH_4BIT;
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break;
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case 0x01:
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ret_val = MV_DDR_DEV_WIDTH_8BIT;
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break;
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case 0x02:
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ret_val = MV_DDR_DEV_WIDTH_16BIT;
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break;
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case 0x03:
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ret_val = MV_DDR_DEV_WIDTH_32BIT;
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break;
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default:
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ret_val = MV_DDR_DEV_WIDTH_LAST;
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}
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return ret_val;
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}
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enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char die_cap = spd_data->byte_fields.byte_4.bit_fields.die_capacity;
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enum mv_ddr_die_capacity ret_val;
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switch (die_cap) {
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case 0x00:
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ret_val = MV_DDR_DIE_CAP_256MBIT;
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break;
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case 0x01:
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ret_val = MV_DDR_DIE_CAP_512MBIT;
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break;
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case 0x02:
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ret_val = MV_DDR_DIE_CAP_1GBIT;
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break;
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case 0x03:
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ret_val = MV_DDR_DIE_CAP_2GBIT;
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break;
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case 0x04:
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ret_val = MV_DDR_DIE_CAP_4GBIT;
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break;
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case 0x05:
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ret_val = MV_DDR_DIE_CAP_8GBIT;
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break;
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case 0x06:
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ret_val = MV_DDR_DIE_CAP_16GBIT;
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break;
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case 0x07:
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ret_val = MV_DDR_DIE_CAP_32GBIT;
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break;
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case 0x08:
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ret_val = MV_DDR_DIE_CAP_12GBIT;
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break;
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case 0x09:
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ret_val = MV_DDR_DIE_CAP_24GBIT;
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break;
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default:
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ret_val = MV_DDR_DIE_CAP_LAST;
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}
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return ret_val;
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}
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unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char mem_mirror = spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping;
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return mem_mirror;
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}
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enum mv_ddr_pkg_rank mv_ddr_spd_pri_bus_width_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char pri_bus_width = spd_data->byte_fields.byte_13.bit_fields.primary_bus_width;
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enum mv_ddr_pri_bus_width ret_val;
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switch (pri_bus_width) {
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case 0x00:
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ret_val = MV_DDR_PRI_BUS_WIDTH_8;
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break;
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case 0x01:
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ret_val = MV_DDR_PRI_BUS_WIDTH_16;
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break;
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case 0x02:
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ret_val = MV_DDR_PRI_BUS_WIDTH_32;
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break;
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case 0x03:
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ret_val = MV_DDR_PRI_BUS_WIDTH_64;
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break;
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default:
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ret_val = MV_DDR_PRI_BUS_WIDTH_LAST;
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}
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return ret_val;
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}
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enum mv_ddr_pkg_rank mv_ddr_spd_bus_width_ext_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char bus_width_ext = spd_data->byte_fields.byte_13.bit_fields.bus_width_ext;
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enum mv_ddr_bus_width_ext ret_val;
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switch (bus_width_ext) {
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case 0x00:
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ret_val = MV_DDR_BUS_WIDTH_EXT_0;
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break;
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case 0x01:
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ret_val = MV_DDR_BUS_WIDTH_EXT_8;
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break;
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default:
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ret_val = MV_DDR_BUS_WIDTH_EXT_LAST;
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}
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return ret_val;
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}
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static enum mv_ddr_pkg_rank mv_ddr_spd_pkg_rank_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char pkg_rank = spd_data->byte_fields.byte_12.bit_fields.dimm_pkg_ranks_num;
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enum mv_ddr_pkg_rank ret_val;
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switch (pkg_rank) {
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case 0x00:
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ret_val = MV_DDR_PKG_RANK_1;
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break;
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case 0x01:
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ret_val = MV_DDR_PKG_RANK_2;
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break;
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case 0x02:
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ret_val = MV_DDR_PKG_RANK_3;
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break;
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case 0x03:
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ret_val = MV_DDR_PKG_RANK_4;
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break;
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case 0x04:
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ret_val = MV_DDR_PKG_RANK_5;
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break;
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case 0x05:
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ret_val = MV_DDR_PKG_RANK_6;
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break;
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case 0x06:
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ret_val = MV_DDR_PKG_RANK_7;
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break;
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case 0x07:
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ret_val = MV_DDR_PKG_RANK_8;
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break;
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default:
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ret_val = MV_DDR_PKG_RANK_LAST;
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}
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return ret_val;
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}
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static enum mv_ddr_die_count mv_ddr_spd_die_count_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char die_count = spd_data->byte_fields.byte_6.bit_fields.die_count;
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enum mv_ddr_die_count ret_val;
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switch (die_count) {
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case 0x00:
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ret_val = MV_DDR_DIE_CNT_1;
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break;
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case 0x01:
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ret_val = MV_DDR_DIE_CNT_2;
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break;
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case 0x02:
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ret_val = MV_DDR_DIE_CNT_3;
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break;
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case 0x03:
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ret_val = MV_DDR_DIE_CNT_4;
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break;
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case 0x04:
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ret_val = MV_DDR_DIE_CNT_5;
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break;
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case 0x05:
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ret_val = MV_DDR_DIE_CNT_6;
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break;
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case 0x06:
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ret_val = MV_DDR_DIE_CNT_7;
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break;
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case 0x07:
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ret_val = MV_DDR_DIE_CNT_8;
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break;
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default:
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ret_val = MV_DDR_DIE_CNT_LAST;
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}
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return ret_val;
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}
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unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char cs_bit_mask = 0x0;
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enum mv_ddr_pkg_rank pkg_rank = mv_ddr_spd_pkg_rank_get(spd_data);
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enum mv_ddr_die_count die_cnt = mv_ddr_spd_die_count_get(spd_data);
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if (pkg_rank == MV_DDR_PKG_RANK_1 && die_cnt == MV_DDR_DIE_CNT_1)
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cs_bit_mask = 0x1;
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else if (pkg_rank == MV_DDR_PKG_RANK_1 && die_cnt == MV_DDR_DIE_CNT_2)
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cs_bit_mask = 0x3;
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else if (pkg_rank == MV_DDR_PKG_RANK_2 && die_cnt == MV_DDR_DIE_CNT_1)
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cs_bit_mask = 0x3;
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else if (pkg_rank == MV_DDR_PKG_RANK_2 && die_cnt == MV_DDR_DIE_CNT_2)
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cs_bit_mask = 0xf;
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return cs_bit_mask;
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}
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unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char dev_type = spd_data->byte_fields.byte_2;
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return dev_type;
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}
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unsigned char mv_ddr_spd_module_type_get(union mv_ddr_spd_data *spd_data)
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{
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unsigned char module_type = spd_data->byte_fields.byte_3.bit_fields.module_type;
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return module_type;
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}
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