mirror of
https://github.com/AsahiLinux/u-boot
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393cb36199
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15 based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15 based SoC's will be sub-classified as Exynos4 and Exynos5 respectively. In order to better adapt and reuse code across various upcoming Samsung Exynos based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix are renamed as exynos4/EXYNOS4. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
395 lines
8.4 KiB
ArmAsm
395 lines
8.4 KiB
ArmAsm
/*
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* Lowlevel setup for universal board based on EXYNOS4210
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*
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* Copyright (C) 2010 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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/*
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* Register usages:
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*
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* r5 has zero always
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* r7 has GPIO part1 base 0x11400000
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* r6 has GPIO part2 base 0x11000000
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*/
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.globl lowlevel_init
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lowlevel_init:
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mov r11, lr
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/* r5 has always zero */
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mov r5, #0
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ldr r7, =EXYNOS4_GPIO_PART1_BASE
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ldr r6, =EXYNOS4_GPIO_PART2_BASE
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/* System Timer */
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ldr r0, =EXYNOS4_SYSTIMER_BASE
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ldr r1, =0x5000
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str r1, [r0, #0x0]
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ldr r1, =0xffffffff
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str r1, [r0, #0x8]
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ldr r1, =0x49
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str r1, [r0, #0x4]
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/* PMIC manual reset */
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/* nPOWER: XEINT_23: GPX2[7] */
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add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET
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ldr r1, [r0, #0x0]
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bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
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orr r1, r1, #(0x1 << 28) @ Output
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str r1, [r0, #0x0]
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ldr r1, [r0, #0x4]
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orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
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str r1, [r0, #0x4]
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/* init system clock */
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bl system_clock_init
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/* Disable Watchdog */
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ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000
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str r5, [r0]
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/* UART */
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bl uart_asm_init
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/* PMU init */
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bl system_power_init
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bl tzpc_init
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mov lr, r11
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mov pc, lr
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nop
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nop
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nop
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/*
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* uart_asm_init: Initialize UART's pins
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*/
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uart_asm_init:
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/*
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* setup UART0-UART4 GPIOs (part1)
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* GPA1CON[3] = I2C_3_SCL (3)
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* GPA1CON[2] = I2C_3_SDA (3)
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*/
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mov r0, r7
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ldr r1, =0x22222222
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str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
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ldr r1, =0x00223322
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str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
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/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
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add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET
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ldr r1, [r0, #0x0]
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bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
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orr r1, r1, #(0x1 << 28)
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str r1, [r0, #0x0]
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ldr r1, [r0, #0x8]
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bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
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orr r1, r1, #(0x3 << 14) @ Pull-up enabled
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str r1, [r0, #0x8]
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ldr r1, [r0, #0x4]
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orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
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str r1, [r0, #0x4]
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mov pc, lr
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nop
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nop
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nop
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system_clock_init:
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ldr r0, =EXYNOS4_CLOCK_BASE
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/* APLL(1), MPLL(1), CORE(0), HPM(0) */
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ldr r1, =0x0101
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ldr r2, =0x14200 @ CLK_SRC_CPU
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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1: subs r1, r1, #1
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bne 1b
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/*
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* CLK_SRC_TOP0
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* MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166
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* MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL
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* MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL
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*/
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ldr r1, =0x10000110
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ldr r2, =0x0C210 @ CLK_SRC_TOP
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str r1, [r0, r2]
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/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
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ldr r1, =0x0066666
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ldr r2, =0x0C240 @ CLK_SRC_FSYS
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str r1, [r0, r2]
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/* UART[0:5], PWM: SCLKMPLL(6) */
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ldr r1, =0x6666666
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ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
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str r1, [r0, r2]
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/* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
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ldr r1, =0x0133730
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ldr r2, =0x14500 @ CLK_DIV_CPU0
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str r1, [r0, r2]
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/* CPU1: COPY, HPM */
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ldr r1, =0x03
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ldr r2, =0x14504 @ CLK_DIV_CPU1
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str r1, [r0, r2]
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/* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
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ldr r1, =0x13111113
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ldr r2, =0x10500 @ CLK_DIV_DMC0
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str r1, [r0, r2]
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/* DMC1: PWI, DVSEM, DPM */
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ldr r1, =0x01010100
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ldr r2, =0x10504 @ CLK_DIV_DMC1
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str r1, [r0, r2]
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/* LEFTBUS: GDL, GPL */
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ldr r1, =0x13
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ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
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str r1, [r0, r2]
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/* RIGHHTBUS: GDR, GPR */
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ldr r1, =0x13
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ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
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str r1, [r0, r2]
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/*
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* CLK_DIV_TOP
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* ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
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* ACLK_200, ACLK_100, ACLK_160, ACLK_133,
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*/
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ldr r1, =0x00005473
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ldr r2, =0x0C510 @ CLK_DIV_TOP
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str r1, [r0, r2]
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/* MMC[0:1] */
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ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
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ldr r2, =0x0C544 @ CLK_DIV_FSYS1
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str r1, [r0, r2]
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/* MMC[2:3] */
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ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
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ldr r2, =0x0C548 @ CLK_DIV_FSYS2
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str r1, [r0, r2]
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/* MMC4 */
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ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
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ldr r2, =0x0C54C @ CLK_DIV_FSYS3
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str r1, [r0, r2]
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/* UART[0:5] */
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ldr r1, =0x774777
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ldr r2, =0x0C550 @ CLK_DIV_PERIL0
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str r1, [r0, r2]
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/* SLIMBUS: ???, PWM */
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ldr r1, =0x8
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ldr r2, =0x0C55C @ CLK_DIV_PERIL3
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str r1, [r0, r2]
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/* PLL Setting */
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ldr r1, =0x1C20
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ldr r2, =0x14000 @ APLL_LOCK
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str r1, [r0, r2]
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ldr r2, =0x14008 @ MPLL_LOCK
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str r1, [r0, r2]
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ldr r2, =0x0C010 @ EPLL_LOCK
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str r1, [r0, r2]
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ldr r2, =0x0C020 @ VPLL_LOCK
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str r1, [r0, r2]
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/* APLL */
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ldr r1, =0x8000001c
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ldr r2, =0x14104 @ APLL_CON1
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str r1, [r0, r2]
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ldr r1, =0x80c80601 @ 800MHz
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ldr r2, =0x14100 @ APLL_CON0
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str r1, [r0, r2]
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/* MPLL */
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ldr r1, =0x8000001C
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ldr r2, =0x1410C @ MPLL_CON1
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str r1, [r0, r2]
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ldr r1, =0x80c80601 @ 800MHz
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ldr r2, =0x14108 @ MPLL_CON0
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str r1, [r0, r2]
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/* EPLL */
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ldr r1, =0x0
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ldr r2, =0x0C114 @ EPLL_CON1
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str r1, [r0, r2]
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ldr r1, =0x80300302 @ 96MHz
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ldr r2, =0x0C110 @ EPLL_CON0
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str r1, [r0, r2]
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/* VPLL */
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ldr r1, =0x11000400
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ldr r2, =0x0C124 @ VPLL_CON1
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str r1, [r0, r2]
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ldr r1, =0x80350302 @ 108MHz
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ldr r2, =0x0C120 @ VPLL_CON0
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str r1, [r0, r2]
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/*
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* SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001
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* Turn off all
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*/
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ldr r1, =0xFFF80000
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ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
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str r1, [r0, r2]
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/* Turn off all */
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ldr r1, =0xFFFFFFC0
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ldr r2, =0x0C924 @ CLK_GATE_IP_VP
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str r1, [r0, r2]
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/* Turn off all */
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ldr r1, =0xFFFFFFE0
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ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
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str r1, [r0, r2]
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/* Turn off all */
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ldr r1, =0xFFFFFFFC
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ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
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str r1, [r0, r2]
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/* Turn off all */
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ldr r1, =0xFFFFFC00
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ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
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str r1, [r0, r2]
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/* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */
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ldr r1, =0xFFFFFFF1
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ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
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str r1, [r0, r2]
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/* Turn off all */
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ldr r1, =0xFFFFFFC0
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ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
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str r1, [r0, r2]
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/*
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* SMMUPCIE[18], NFCON[16] : 1111 1010
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* PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000
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* SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011
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*/
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ldr r1, =0xFFFAB8A3
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ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
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str r1, [r0, r2]
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/* Turn off all */
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ldr r1, =0xFFFFFFFC
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ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
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str r1, [r0, r2]
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/*
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* AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001
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* I2C2[8] : 1111 1110
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*/
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ldr r1, =0xF1FFFEFF
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ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
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str r1, [r0, r2]
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/*
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* KEYIF[16] : 1111 1110
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*/
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ldr r1, =0xFFFEFFFF
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ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
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str r1, [r0, r2]
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/* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */
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ldr r1, =0xFFFFFFD1
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ldr r2, =0x0C970 @ CLK_GATE_BLOCK
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str r1, [r0, r2]
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mov pc, lr
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nop
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nop
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nop
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system_power_init:
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ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000
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ldr r2, =0x330C @ PS_HOLD_CONTROL
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ldr r1, [r0, r2]
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orr r1, r1, #(0x3 << 8) @ Data High, Output En
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str r1, [r0, r2]
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/* Power Down */
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add r2, r0, #0x3000
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str r5, [r2, #0xC20] @ TV_CONFIGURATION
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str r5, [r2, #0xC40] @ MFC_CONFIGURATION
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str r5, [r2, #0xC60] @ G3D_CONFIGURATION
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str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
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str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
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mov pc, lr
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nop
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nop
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nop
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tzpc_init:
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ldr r0, =0x10110000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10120000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10130000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10140000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10150000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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mov pc, lr
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