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https://github.com/AsahiLinux/u-boot
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133fbfa9e6
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
756 lines
19 KiB
C
756 lines
19 KiB
C
/*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Modified by Xianghua Xiao, X.Xiao@motorola.com
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/processor.h>
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#include <ioports.h>
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#include <sata.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <asm/fsl_errata.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_srio.h>
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#include <fsl_usb.h>
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#include <hwconfig.h>
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#include <linux/compiler.h>
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#include "mp.h"
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#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#include <nand.h>
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#include <errno.h>
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#endif
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#include "../../../../drivers/block/fsl_sata.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_QE
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extern qe_iop_conf_t qe_iop_conf_tab[];
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extern void qe_config_iopin(u8 port, u8 pin, int dir,
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int open_drain, int assign);
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extern void qe_init(uint qe_base);
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extern void qe_reset(void);
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static void config_qe_ioports(void)
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{
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u8 port, pin;
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int dir, open_drain, assign;
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int i;
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for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
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port = qe_iop_conf_tab[i].port;
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pin = qe_iop_conf_tab[i].pin;
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dir = qe_iop_conf_tab[i].dir;
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open_drain = qe_iop_conf_tab[i].open_drain;
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assign = qe_iop_conf_tab[i].assign;
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qe_config_iopin(port, pin, dir, open_drain, assign);
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}
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}
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#endif
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#ifdef CONFIG_CPM2
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void config_8560_ioports (volatile ccsr_cpm_t * cpm)
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{
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int portnum;
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for (portnum = 0; portnum < 4; portnum++) {
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uint pmsk = 0,
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ppar = 0,
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psor = 0,
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pdir = 0,
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podr = 0,
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pdat = 0;
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iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
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iop_conf_t *eiopc = iopc + 32;
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uint msk = 1;
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/*
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* NOTE:
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* index 0 refers to pin 31,
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* index 31 refers to pin 0
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*/
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while (iopc < eiopc) {
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if (iopc->conf) {
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pmsk |= msk;
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if (iopc->ppar)
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ppar |= msk;
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if (iopc->psor)
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psor |= msk;
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if (iopc->pdir)
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pdir |= msk;
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if (iopc->podr)
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podr |= msk;
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if (iopc->pdat)
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pdat |= msk;
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}
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msk <<= 1;
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iopc++;
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}
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if (pmsk != 0) {
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volatile ioport_t *iop = ioport_addr (cpm, portnum);
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uint tpmsk = ~pmsk;
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/*
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* the (somewhat confused) paragraph at the
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* bottom of page 35-5 warns that there might
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* be "unknown behaviour" when programming
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* PSORx and PDIRx, if PPARx = 1, so I
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* decided this meant I had to disable the
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* dedicated function first, and enable it
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* last.
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*/
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iop->ppar &= tpmsk;
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iop->psor = (iop->psor & tpmsk) | psor;
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iop->podr = (iop->podr & tpmsk) | podr;
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iop->pdat = (iop->pdat & tpmsk) | pdat;
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iop->pdir = (iop->pdir & tpmsk) | pdir;
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iop->ppar |= ppar;
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}
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}
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}
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#endif
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#ifdef CONFIG_SYS_FSL_CPC
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static void enable_cpc(void)
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{
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int i;
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u32 size = 0;
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cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
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for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
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u32 cpccfg0 = in_be32(&cpc->cpccfg0);
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size += CPC_CFG0_SZ_K(cpccfg0);
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#ifdef CONFIG_RAMBOOT_PBL
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if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
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/* find and disable LAW of SRAM */
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struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
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if (law.index == -1) {
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printf("\nFatal error happened\n");
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return;
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}
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disable_law(law.index);
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clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
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out_be32(&cpc->cpccsr0, 0);
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out_be32(&cpc->cpcsrcr0, 0);
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}
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
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setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
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setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
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setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
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if (has_erratum_a006379()) {
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setbits_be32(&cpc->cpchdbcr0,
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CPC_HDBCR0_SPLRU_LEVEL_EN);
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}
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#endif
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out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
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/* Read back to sync write */
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in_be32(&cpc->cpccsr0);
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}
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puts("Corenet Platform Cache: ");
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print_size(size * 1024, " enabled\n");
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}
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static void invalidate_cpc(void)
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{
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int i;
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cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
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for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
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/* skip CPC when it used as all SRAM */
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if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
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continue;
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/* Flash invalidate the CPC and clear all the locks */
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out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
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while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
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;
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}
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}
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#else
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#define enable_cpc()
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#define invalidate_cpc()
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#endif /* CONFIG_SYS_FSL_CPC */
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map
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* initialize a bunch of registers
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*/
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#ifdef CONFIG_FSL_CORENET
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static void corenet_tb_init(void)
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{
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volatile ccsr_rcpm_t *rcpm =
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(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
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volatile ccsr_pic_t *pic =
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(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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u32 whoami = in_be32(&pic->whoami);
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/* Enable the timebase register for this core */
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out_be32(&rcpm->ctbenrl, (1 << whoami));
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}
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#endif
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void cpu_init_f (void)
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{
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extern void m8560_cpm_reset (void);
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#endif
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#if defined(CONFIG_SECURE_BOOT)
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struct law_entry law;
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#endif
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#ifdef CONFIG_MPC8548
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ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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uint svr = get_svr();
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/*
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* CPU2 errata workaround: A core hang possible while executing
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* a msync instruction and a snoopable transaction from an I/O
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* master tagged to make quick forward progress is present.
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* Fixed in silicon rev 2.1.
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*/
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if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
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out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
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#endif
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disable_tlb(14);
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disable_tlb(15);
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#if defined(CONFIG_SECURE_BOOT)
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/* Disable the LAW created for NOR flash by the PBI commands */
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law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
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if (law.index != -1)
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disable_law(law.index);
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#endif
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#ifdef CONFIG_CPM2
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config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
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#endif
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init_early_memctl_regs();
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#if defined(CONFIG_CPM2)
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m8560_cpm_reset();
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#endif
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#ifdef CONFIG_QE
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/* Config QE ioports */
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config_qe_ioports();
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#endif
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#if defined(CONFIG_FSL_DMA)
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dma_init();
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#endif
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#ifdef CONFIG_FSL_CORENET
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corenet_tb_init();
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#endif
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init_used_tlb_cams();
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/* Invalidate the CPC before DDR gets enabled */
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invalidate_cpc();
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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/* set DCSRCR so that DCSR space is 1G */
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setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
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in_be32(&gur->dcsrcr);
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#endif
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}
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/* Implement a dummy function for those platforms w/o SERDES */
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static void __fsl_serdes__init(void)
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{
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return ;
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}
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__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
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#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
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int enable_cluster_l2(void)
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{
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int i = 0;
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u32 cluster;
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct ccsr_cluster_l2 __iomem *l2cache;
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cluster = in_be32(&gur->tp_cluster[i].lower);
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if (cluster & TP_CLUSTER_EOC)
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return 0;
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/* The first cache has already been set up, so skip it */
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i++;
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/* Look through the remaining clusters, and set up their caches */
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do {
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int j, cluster_valid = 0;
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l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
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cluster = in_be32(&gur->tp_cluster[i].lower);
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/* check that at least one core/accel is enabled in cluster */
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for (j = 0; j < 4; j++) {
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u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
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u32 type = in_be32(&gur->tp_ityp[idx]);
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if (type & TP_ITYP_AV)
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cluster_valid = 1;
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}
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if (cluster_valid) {
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/* set stash ID to (cluster) * 2 + 32 + 1 */
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clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
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printf("enable l2 for cluster %d %p\n", i, l2cache);
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out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
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while ((in_be32(&l2cache->l2csr0)
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& (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
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;
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out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
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}
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i++;
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} while (!(cluster & TP_CLUSTER_EOC));
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return 0;
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}
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#endif
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/*
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* Initialize L2 as cache.
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*
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* The newer 8548, etc, parts have twice as much cache, but
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* use the same bit-encoding as the older 8555, etc, parts.
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*
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*/
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int cpu_init_r(void)
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{
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__maybe_unused u32 svr = get_svr();
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#ifdef CONFIG_SYS_LBC_LCRR
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fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
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#endif
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#ifdef CONFIG_L2_CACHE
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ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
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#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
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struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
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#endif
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#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
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extern int spin_table_compat;
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const char *spin;
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
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ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
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defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
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/*
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* CPU22 and NMG_CPU_A011 share the same workaround.
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* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
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* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
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* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
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* fixed in 2.0. NMG_CPU_A011 is activated by default and can
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* be disabled by hwconfig with syntax:
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*
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* fsl_cpu_a011:disable
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*/
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extern int enable_cpu_a011_workaround;
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#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
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enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
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#else
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char buffer[HWCONFIG_BUFFER_SIZE];
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char *buf = NULL;
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int n, res;
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n = getenv_f("hwconfig", buffer, sizeof(buffer));
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if (n > 0)
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buf = buffer;
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res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
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if (res > 0)
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enable_cpu_a011_workaround = 0;
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else {
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if (n >= HWCONFIG_BUFFER_SIZE) {
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printf("fsl_cpu_a011 was not found. hwconfig variable "
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"may be too long\n");
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}
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enable_cpu_a011_workaround =
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(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
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(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
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}
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#endif
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if (enable_cpu_a011_workaround) {
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flush_dcache();
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mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
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sync();
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}
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
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/*
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* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
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* in write shadow mode. Checking DCWS before setting SPR 976.
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*/
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if (mfspr(L1CSR2) & L1CSR2_DCWS)
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mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
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#endif
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#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
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spin = getenv("spin_table_compat");
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if (spin && (*spin == 'n'))
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spin_table_compat = 0;
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else
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spin_table_compat = 1;
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#endif
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puts ("L2: ");
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#if defined(CONFIG_L2_CACHE)
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volatile uint cache_ctl;
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uint ver;
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u32 l2siz_field;
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ver = SVR_SOC_VER(svr);
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asm("msync;isync");
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cache_ctl = l2cache->l2ctl;
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
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if (cache_ctl & MPC85xx_L2CTL_L2E) {
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/* Clear L2 SRAM memory-mapped base address */
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out_be32(&l2cache->l2srbar0, 0x0);
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out_be32(&l2cache->l2srbar1, 0x0);
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/* set MBECCDIS=0, SBECCDIS=0 */
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clrbits_be32(&l2cache->l2errdis,
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(MPC85xx_L2ERRDIS_MBECC |
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MPC85xx_L2ERRDIS_SBECC));
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/* set L2E=0, L2SRAM=0 */
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clrbits_be32(&l2cache->l2ctl,
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(MPC85xx_L2CTL_L2E |
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MPC85xx_L2CTL_L2SRAM_ENTIRE));
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}
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#endif
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l2siz_field = (cache_ctl >> 28) & 0x3;
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switch (l2siz_field) {
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case 0x0:
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printf(" unknown size (0x%08x)\n", cache_ctl);
|
|
return -1;
|
|
break;
|
|
case 0x1:
|
|
if (ver == SVR_8540 || ver == SVR_8560 ||
|
|
ver == SVR_8541 || ver == SVR_8555) {
|
|
puts("128 KiB ");
|
|
/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
|
|
cache_ctl = 0xc4000000;
|
|
} else {
|
|
puts("256 KiB ");
|
|
cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
|
|
}
|
|
break;
|
|
case 0x2:
|
|
if (ver == SVR_8540 || ver == SVR_8560 ||
|
|
ver == SVR_8541 || ver == SVR_8555) {
|
|
puts("256 KiB ");
|
|
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
|
|
cache_ctl = 0xc8000000;
|
|
} else {
|
|
puts("512 KiB ");
|
|
/* set L2E=1, L2I=1, & L2SRAM=0 */
|
|
cache_ctl = 0xc0000000;
|
|
}
|
|
break;
|
|
case 0x3:
|
|
puts("1024 KiB ");
|
|
/* set L2E=1, L2I=1, & L2SRAM=0 */
|
|
cache_ctl = 0xc0000000;
|
|
break;
|
|
}
|
|
|
|
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
|
|
puts("already enabled");
|
|
#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
|
|
u32 l2srbar = l2cache->l2srbar0;
|
|
if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
|
|
&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
|
|
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
|
|
l2cache->l2srbar0 = l2srbar;
|
|
printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
|
|
}
|
|
#endif /* CONFIG_SYS_INIT_L2_ADDR */
|
|
puts("\n");
|
|
} else {
|
|
asm("msync;isync");
|
|
l2cache->l2ctl = cache_ctl; /* invalidate & enable */
|
|
asm("msync;isync");
|
|
puts("enabled\n");
|
|
}
|
|
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
|
|
if (SVR_SOC_VER(svr) == SVR_P2040) {
|
|
puts("N/A\n");
|
|
goto skip_l2;
|
|
}
|
|
|
|
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
|
|
|
|
/* invalidate the L2 cache */
|
|
mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
|
|
while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
|
|
;
|
|
|
|
#ifdef CONFIG_SYS_CACHE_STASHING
|
|
/* set stash id to (coreID) * 2 + 32 + L2 (1) */
|
|
mtspr(SPRN_L2CSR1, (32 + 1));
|
|
#endif
|
|
|
|
/* enable the cache */
|
|
mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
|
|
|
|
if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
|
|
while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
|
|
;
|
|
print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
|
|
}
|
|
|
|
skip_l2:
|
|
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
|
|
if (l2cache->l2csr0 & L2CSR0_L2E)
|
|
print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
|
|
" enabled\n");
|
|
|
|
enable_cluster_l2();
|
|
#else
|
|
puts("disabled\n");
|
|
#endif
|
|
|
|
enable_cpc();
|
|
|
|
#ifndef CONFIG_SYS_FSL_NO_SERDES
|
|
/* needs to be in ram since code uses global static vars */
|
|
fsl_serdes_init();
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
|
|
#define MCFGR_AXIPIPE 0x000000f0
|
|
if (IS_SVR_REV(svr, 1, 0))
|
|
clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
|
|
if (IS_SVR_REV(svr, 1, 0)) {
|
|
int i;
|
|
__be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
|
|
|
|
for (i = 0; i < 12; i++) {
|
|
p += i + (i > 5 ? 11 : 0);
|
|
out_be32(p, 0x2);
|
|
}
|
|
p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
|
|
out_be32(p, 0x34);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_SRIO
|
|
srio_init();
|
|
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
|
|
char *s = getenv("bootmaster");
|
|
if (s) {
|
|
if (!strcmp(s, "SRIO1")) {
|
|
srio_boot_master(1);
|
|
srio_boot_master_release_slave(1);
|
|
}
|
|
if (!strcmp(s, "SRIO2")) {
|
|
srio_boot_master(2);
|
|
srio_boot_master_release_slave(2);
|
|
}
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_MP)
|
|
setup_mp();
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
|
|
{
|
|
if (SVR_MAJ(svr) < 3) {
|
|
void *p;
|
|
p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
|
|
setbits_be32(p, 1 << (31 - 14));
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_LBC_LCRR
|
|
/*
|
|
* Modify the CLKDIV field of LCRR register to improve the writing
|
|
* speed for NOR flash.
|
|
*/
|
|
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
|
|
__raw_readl(&lbc->lcrr);
|
|
isync();
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
|
|
udelay(100);
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
{
|
|
struct ccsr_usb_phy __iomem *usb_phy1 =
|
|
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
|
|
out_be32(&usb_phy1->usb_enable_override,
|
|
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
|
{
|
|
struct ccsr_usb_phy __iomem *usb_phy2 =
|
|
(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
|
|
out_be32(&usb_phy2->usb_enable_override,
|
|
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
|
|
/* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
|
|
* multi-bit ECC errors which has impact on performance, so software
|
|
* should disable all ECC reporting from USB1 and USB2.
|
|
*/
|
|
if (IS_SVR_REV(get_svr(), 1, 0)) {
|
|
struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
|
|
(CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
|
|
setbits_be32(&dcfg->ecccr1,
|
|
(DCSR_DCFG_ECC_DISABLE_USB1 |
|
|
DCSR_DCFG_ECC_DISABLE_USB2));
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
|
|
struct ccsr_usb_phy __iomem *usb_phy =
|
|
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
|
|
setbits_be32(&usb_phy->pllprg[1],
|
|
CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
|
|
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
|
|
CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
|
|
CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
|
|
setbits_be32(&usb_phy->port1.ctrl,
|
|
CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
|
|
setbits_be32(&usb_phy->port1.drvvbuscfg,
|
|
CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
|
|
setbits_be32(&usb_phy->port1.pwrfltcfg,
|
|
CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
|
|
setbits_be32(&usb_phy->port2.ctrl,
|
|
CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
|
|
setbits_be32(&usb_phy->port2.drvvbuscfg,
|
|
CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
|
|
setbits_be32(&usb_phy->port2.pwrfltcfg,
|
|
CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
|
|
#endif
|
|
|
|
#ifdef CONFIG_FMAN_ENET
|
|
fman_enet_init();
|
|
#endif
|
|
|
|
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
|
|
/*
|
|
* For P1022/1013 Rev1.0 silicon, after power on SATA host
|
|
* controller is configured in legacy mode instead of the
|
|
* expected enterprise mode. Software needs to clear bit[28]
|
|
* of HControl register to change to enterprise mode from
|
|
* legacy mode. We assume that the controller is offline.
|
|
*/
|
|
if (IS_SVR_REV(svr, 1, 0) &&
|
|
((SVR_SOC_VER(svr) == SVR_P1022) ||
|
|
(SVR_SOC_VER(svr) == SVR_P1013))) {
|
|
fsl_sata_reg_t *reg;
|
|
|
|
/* first SATA controller */
|
|
reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
|
|
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
|
|
|
|
/* second SATA controller */
|
|
reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
|
|
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
|
|
}
|
|
#endif
|
|
|
|
|
|
return 0;
|
|
}
|
|
|
|
extern void setup_ivors(void);
|
|
|
|
void arch_preboot_os(void)
|
|
{
|
|
u32 msr;
|
|
|
|
/*
|
|
* We are changing interrupt offsets and are about to boot the OS so
|
|
* we need to make sure we disable all async interrupts. EE is already
|
|
* disabled by the time we get called.
|
|
*/
|
|
msr = mfmsr();
|
|
msr &= ~(MSR_ME|MSR_CE);
|
|
mtmsr(msr);
|
|
|
|
setup_ivors();
|
|
}
|
|
|
|
#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
|
|
int sata_initialize(void)
|
|
{
|
|
if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
|
|
return __sata_initialize();
|
|
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
void cpu_secondary_init_r(void)
|
|
{
|
|
#ifdef CONFIG_QE
|
|
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
|
|
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
|
int ret;
|
|
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
|
|
|
|
/* load QE firmware from NAND flash to DDR first */
|
|
ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
|
|
&fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
|
|
|
|
if (ret && ret == -EUCLEAN) {
|
|
printf ("NAND read for QE firmware at offset %x failed %d\n",
|
|
CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
|
|
}
|
|
#endif
|
|
qe_init(qe_base);
|
|
qe_reset();
|
|
#endif
|
|
}
|