mirror of
https://github.com/AsahiLinux/u-boot
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80af39842e
Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/arch/device.h>
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#include <asm/arch/tnc.h>
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#include <asm/fsp/fsp_support.h>
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#include <asm/processor.h>
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static void unprotect_spi_flash(void)
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{
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u32 bc;
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bc = x86_pci_read_config32(TNC_LPC, 0xd8);
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bc |= 0x1; /* unprotect the flash */
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x86_pci_write_config32(TNC_LPC, 0xd8, bc);
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}
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static void __maybe_unused disable_igd(void)
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{
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/*
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* According to Atom E6xx datasheet, setting VGA Disable (bit17)
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* of Graphics Controller register (offset 0x50) prevents IGD
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* (D2:F0) from reporting itself as a VGA display controller
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* class in the PCI configuration space, and should also prevent
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* it from responding to VGA legacy memory range and I/O addresses.
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*
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* However test result shows that with just VGA Disable bit set and
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* a PCIe graphics card connected to one of the PCIe controllers on
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* the E6xx, accessing the VGA legacy space still causes system hang.
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* After a number of attempts, it turns out besides VGA Disable bit,
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* the SDVO (D3:F0) device should be disabled to make it work.
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*
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* To simplify, use the Function Disable register (offset 0xc4)
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* to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
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* two devices will be completely disabled (invisible in the PCI
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* configuration space) unless a system reset is performed.
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*/
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x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE);
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x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE);
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}
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int arch_cpu_init(void)
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{
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int ret;
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post_code(POST_CPU_INIT);
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ret = x86_cpu_init_f();
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if (ret)
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return ret;
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return 0;
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}
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int arch_early_init_r(void)
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{
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#ifdef CONFIG_DISABLE_IGD
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disable_igd();
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#endif
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return 0;
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}
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void cpu_irq_init(void)
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{
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struct tnc_rcba *rcba;
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u32 base;
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base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
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base &= ~MEM_BAR_EN;
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rcba = (struct tnc_rcba *)base;
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/* Make sure all internal PCI devices are using INTA */
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writel(INTA, &rcba->d02ip);
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writel(INTA, &rcba->d03ip);
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writel(INTA, &rcba->d27ip);
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writel(INTA, &rcba->d31ip);
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writel(INTA, &rcba->d23ip);
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writel(INTA, &rcba->d24ip);
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writel(INTA, &rcba->d25ip);
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writel(INTA, &rcba->d26ip);
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/*
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* Route TunnelCreek PCI device interrupt pin to PIRQ
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*
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* Since PCIe downstream ports received INTx are routed to PIRQ
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* A/B/C/D directly and not configurable, we have to route PCIe
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* root ports' INTx to PIRQ A/B/C/D as well. For other devices
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* on TunneCreek, route them to PIRQ E/F/G/H.
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*/
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writew(PIRQE, &rcba->d02ir);
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writew(PIRQF, &rcba->d03ir);
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writew(PIRQG, &rcba->d27ir);
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writew(PIRQH, &rcba->d31ir);
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writew(PIRQA, &rcba->d23ir);
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writew(PIRQB, &rcba->d24ir);
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writew(PIRQC, &rcba->d25ir);
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writew(PIRQD, &rcba->d26ir);
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}
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int arch_misc_init(void)
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{
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unprotect_spi_flash();
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return pirq_init();
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}
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