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558 lines
24 KiB
C
558 lines
24 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef DT_BINDINGS_RSCRC_IMX_H
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#define DT_BINDINGS_RSCRC_IMX_H
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/*!
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* These defines are used to indicate a resource. Resources include peripherals
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* and bus masters (but not memory regions). Note items from list should
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* never be changed or removed (only added to at the end of the list).
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*/
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#define SC_R_A53 0
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#define SC_R_A53_0 1
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#define SC_R_A53_1 2
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#define SC_R_A53_2 3
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#define SC_R_A53_3 4
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#define SC_R_A72 5
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#define SC_R_A72_0 6
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#define SC_R_A72_1 7
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#define SC_R_A72_2 8
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#define SC_R_A72_3 9
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#define SC_R_CCI 10
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#define SC_R_DB 11
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#define SC_R_DRC_0 12
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#define SC_R_DRC_1 13
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#define SC_R_GIC_SMMU 14
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#define SC_R_IRQSTR_M4_0 15
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#define SC_R_IRQSTR_M4_1 16
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#define SC_R_SMMU 17
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#define SC_R_GIC 18
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#define SC_R_DC_0_BLIT0 19
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#define SC_R_DC_0_BLIT1 20
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#define SC_R_DC_0_BLIT2 21
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#define SC_R_DC_0_BLIT_OUT 22
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#define SC_R_DC_0_CAPTURE0 23
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#define SC_R_DC_0_CAPTURE1 24
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#define SC_R_DC_0_WARP 25
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#define SC_R_DC_0_INTEGRAL0 26
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#define SC_R_DC_0_INTEGRAL1 27
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#define SC_R_DC_0_VIDEO0 28
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#define SC_R_DC_0_VIDEO1 29
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#define SC_R_DC_0_FRAC0 30
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#define SC_R_DC_0_FRAC1 31
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#define SC_R_DC_0 32
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#define SC_R_GPU_2_PID0 33
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#define SC_R_DC_0_PLL_0 34
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#define SC_R_DC_0_PLL_1 35
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#define SC_R_DC_1_BLIT0 36
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#define SC_R_DC_1_BLIT1 37
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#define SC_R_DC_1_BLIT2 38
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#define SC_R_DC_1_BLIT_OUT 39
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#define SC_R_DC_1_CAPTURE0 40
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#define SC_R_DC_1_CAPTURE1 41
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#define SC_R_DC_1_WARP 42
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#define SC_R_DC_1_INTEGRAL0 43
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#define SC_R_DC_1_INTEGRAL1 44
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#define SC_R_DC_1_VIDEO0 45
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#define SC_R_DC_1_VIDEO1 46
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#define SC_R_DC_1_FRAC0 47
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#define SC_R_DC_1_FRAC1 48
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#define SC_R_DC_1 49
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#define SC_R_GPU_3_PID0 50
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#define SC_R_DC_1_PLL_0 51
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#define SC_R_DC_1_PLL_1 52
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#define SC_R_SPI_0 53
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#define SC_R_SPI_1 54
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#define SC_R_SPI_2 55
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#define SC_R_SPI_3 56
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#define SC_R_UART_0 57
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#define SC_R_UART_1 58
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#define SC_R_UART_2 59
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#define SC_R_UART_3 60
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#define SC_R_UART_4 61
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#define SC_R_EMVSIM_0 62
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#define SC_R_EMVSIM_1 63
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#define SC_R_DMA_0_CH0 64
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#define SC_R_DMA_0_CH1 65
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#define SC_R_DMA_0_CH2 66
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#define SC_R_DMA_0_CH3 67
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#define SC_R_DMA_0_CH4 68
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#define SC_R_DMA_0_CH5 69
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#define SC_R_DMA_0_CH6 70
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#define SC_R_DMA_0_CH7 71
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#define SC_R_DMA_0_CH8 72
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#define SC_R_DMA_0_CH9 73
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#define SC_R_DMA_0_CH10 74
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#define SC_R_DMA_0_CH11 75
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#define SC_R_DMA_0_CH12 76
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#define SC_R_DMA_0_CH13 77
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#define SC_R_DMA_0_CH14 78
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#define SC_R_DMA_0_CH15 79
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#define SC_R_DMA_0_CH16 80
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#define SC_R_DMA_0_CH17 81
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#define SC_R_DMA_0_CH18 82
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#define SC_R_DMA_0_CH19 83
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#define SC_R_DMA_0_CH20 84
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#define SC_R_DMA_0_CH21 85
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#define SC_R_DMA_0_CH22 86
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#define SC_R_DMA_0_CH23 87
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#define SC_R_DMA_0_CH24 88
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#define SC_R_DMA_0_CH25 89
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#define SC_R_DMA_0_CH26 90
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#define SC_R_DMA_0_CH27 91
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#define SC_R_DMA_0_CH28 92
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#define SC_R_DMA_0_CH29 93
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#define SC_R_DMA_0_CH30 94
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#define SC_R_DMA_0_CH31 95
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#define SC_R_I2C_0 96
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#define SC_R_I2C_1 97
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#define SC_R_I2C_2 98
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#define SC_R_I2C_3 99
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#define SC_R_I2C_4 100
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#define SC_R_ADC_0 101
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#define SC_R_ADC_1 102
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#define SC_R_FTM_0 103
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#define SC_R_FTM_1 104
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#define SC_R_CAN_0 105
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#define SC_R_CAN_1 106
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#define SC_R_CAN_2 107
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#define SC_R_DMA_1_CH0 108
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#define SC_R_DMA_1_CH1 109
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#define SC_R_DMA_1_CH2 110
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#define SC_R_DMA_1_CH3 111
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#define SC_R_DMA_1_CH4 112
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#define SC_R_DMA_1_CH5 113
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#define SC_R_DMA_1_CH6 114
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#define SC_R_DMA_1_CH7 115
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#define SC_R_DMA_1_CH8 116
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#define SC_R_DMA_1_CH9 117
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#define SC_R_DMA_1_CH10 118
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#define SC_R_DMA_1_CH11 119
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#define SC_R_DMA_1_CH12 120
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#define SC_R_DMA_1_CH13 121
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#define SC_R_DMA_1_CH14 122
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#define SC_R_DMA_1_CH15 123
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#define SC_R_DMA_1_CH16 124
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#define SC_R_DMA_1_CH17 125
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#define SC_R_DMA_1_CH18 126
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#define SC_R_DMA_1_CH19 127
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#define SC_R_DMA_1_CH20 128
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#define SC_R_DMA_1_CH21 129
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#define SC_R_DMA_1_CH22 130
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#define SC_R_DMA_1_CH23 131
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#define SC_R_DMA_1_CH24 132
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#define SC_R_DMA_1_CH25 133
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#define SC_R_DMA_1_CH26 134
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#define SC_R_DMA_1_CH27 135
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#define SC_R_DMA_1_CH28 136
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#define SC_R_DMA_1_CH29 137
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#define SC_R_DMA_1_CH30 138
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#define SC_R_DMA_1_CH31 139
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#define SC_R_UNUSED1 140
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#define SC_R_UNUSED2 141
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#define SC_R_UNUSED3 142
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#define SC_R_UNUSED4 143
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#define SC_R_GPU_0_PID0 144
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#define SC_R_GPU_0_PID1 145
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#define SC_R_GPU_0_PID2 146
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#define SC_R_GPU_0_PID3 147
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#define SC_R_GPU_1_PID0 148
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#define SC_R_GPU_1_PID1 149
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#define SC_R_GPU_1_PID2 150
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#define SC_R_GPU_1_PID3 151
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#define SC_R_PCIE_A 152
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#define SC_R_SERDES_0 153
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#define SC_R_MATCH_0 154
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#define SC_R_MATCH_1 155
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#define SC_R_MATCH_2 156
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#define SC_R_MATCH_3 157
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#define SC_R_MATCH_4 158
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#define SC_R_MATCH_5 159
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#define SC_R_MATCH_6 160
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#define SC_R_MATCH_7 161
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#define SC_R_MATCH_8 162
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#define SC_R_MATCH_9 163
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#define SC_R_MATCH_10 164
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#define SC_R_MATCH_11 165
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#define SC_R_MATCH_12 166
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#define SC_R_MATCH_13 167
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#define SC_R_MATCH_14 168
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#define SC_R_PCIE_B 169
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#define SC_R_SATA_0 170
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#define SC_R_SERDES_1 171
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#define SC_R_HSIO_GPIO 172
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#define SC_R_MATCH_15 173
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#define SC_R_MATCH_16 174
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#define SC_R_MATCH_17 175
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#define SC_R_MATCH_18 176
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#define SC_R_MATCH_19 177
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#define SC_R_MATCH_20 178
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#define SC_R_MATCH_21 179
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#define SC_R_MATCH_22 180
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#define SC_R_MATCH_23 181
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#define SC_R_MATCH_24 182
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#define SC_R_MATCH_25 183
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#define SC_R_MATCH_26 184
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#define SC_R_MATCH_27 185
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#define SC_R_MATCH_28 186
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#define SC_R_LCD_0 187
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#define SC_R_LCD_0_PWM_0 188
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#define SC_R_LCD_0_I2C_0 189
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#define SC_R_LCD_0_I2C_1 190
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#define SC_R_PWM_0 191
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#define SC_R_PWM_1 192
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#define SC_R_PWM_2 193
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#define SC_R_PWM_3 194
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#define SC_R_PWM_4 195
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#define SC_R_PWM_5 196
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#define SC_R_PWM_6 197
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#define SC_R_PWM_7 198
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#define SC_R_GPIO_0 199
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#define SC_R_GPIO_1 200
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#define SC_R_GPIO_2 201
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#define SC_R_GPIO_3 202
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#define SC_R_GPIO_4 203
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#define SC_R_GPIO_5 204
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#define SC_R_GPIO_6 205
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#define SC_R_GPIO_7 206
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#define SC_R_GPT_0 207
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#define SC_R_GPT_1 208
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#define SC_R_GPT_2 209
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#define SC_R_GPT_3 210
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#define SC_R_GPT_4 211
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#define SC_R_KPP 212
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#define SC_R_MU_0A 213
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#define SC_R_MU_1A 214
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#define SC_R_MU_2A 215
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#define SC_R_MU_3A 216
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#define SC_R_MU_4A 217
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#define SC_R_MU_5A 218
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#define SC_R_MU_6A 219
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#define SC_R_MU_7A 220
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#define SC_R_MU_8A 221
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#define SC_R_MU_9A 222
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#define SC_R_MU_10A 223
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#define SC_R_MU_11A 224
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#define SC_R_MU_12A 225
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#define SC_R_MU_13A 226
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#define SC_R_MU_5B 227
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#define SC_R_MU_6B 228
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#define SC_R_MU_7B 229
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#define SC_R_MU_8B 230
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#define SC_R_MU_9B 231
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#define SC_R_MU_10B 232
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#define SC_R_MU_11B 233
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#define SC_R_MU_12B 234
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#define SC_R_MU_13B 235
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#define SC_R_ROM_0 236
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#define SC_R_FSPI_0 237
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#define SC_R_FSPI_1 238
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#define SC_R_IEE 239
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#define SC_R_IEE_R0 240
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#define SC_R_IEE_R1 241
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#define SC_R_IEE_R2 242
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#define SC_R_IEE_R3 243
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#define SC_R_IEE_R4 244
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#define SC_R_IEE_R5 245
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#define SC_R_IEE_R6 246
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#define SC_R_IEE_R7 247
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#define SC_R_SDHC_0 248
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#define SC_R_SDHC_1 249
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#define SC_R_SDHC_2 250
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#define SC_R_ENET_0 251
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#define SC_R_ENET_1 252
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#define SC_R_MLB_0 253
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#define SC_R_DMA_2_CH0 254
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#define SC_R_DMA_2_CH1 255
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#define SC_R_DMA_2_CH2 256
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#define SC_R_DMA_2_CH3 257
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#define SC_R_DMA_2_CH4 258
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#define SC_R_USB_0 259
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#define SC_R_USB_1 260
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#define SC_R_USB_0_PHY 261
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#define SC_R_USB_2 262
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#define SC_R_USB_2_PHY 263
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#define SC_R_DTCP 264
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#define SC_R_NAND 265
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#define SC_R_LVDS_0 266
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#define SC_R_LVDS_0_PWM_0 267
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#define SC_R_LVDS_0_I2C_0 268
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#define SC_R_LVDS_0_I2C_1 269
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#define SC_R_LVDS_1 270
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#define SC_R_LVDS_1_PWM_0 271
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#define SC_R_LVDS_1_I2C_0 272
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#define SC_R_LVDS_1_I2C_1 273
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#define SC_R_LVDS_2 274
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#define SC_R_LVDS_2_PWM_0 275
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#define SC_R_LVDS_2_I2C_0 276
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#define SC_R_LVDS_2_I2C_1 277
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#define SC_R_M4_0_PID0 278
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#define SC_R_M4_0_PID1 279
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#define SC_R_M4_0_PID2 280
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#define SC_R_M4_0_PID3 281
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#define SC_R_M4_0_PID4 282
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#define SC_R_M4_0_RGPIO 283
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#define SC_R_M4_0_SEMA42 284
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#define SC_R_M4_0_TPM 285
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#define SC_R_M4_0_PIT 286
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#define SC_R_M4_0_UART 287
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#define SC_R_M4_0_I2C 288
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#define SC_R_M4_0_INTMUX 289
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#define SC_R_M4_0_SIM 290
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#define SC_R_M4_0_WDOG 291
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#define SC_R_M4_0_MU_0B 292
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#define SC_R_M4_0_MU_0A0 293
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#define SC_R_M4_0_MU_0A1 294
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#define SC_R_M4_0_MU_0A2 295
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#define SC_R_M4_0_MU_0A3 296
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#define SC_R_M4_0_MU_1A 297
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#define SC_R_M4_1_PID0 298
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#define SC_R_M4_1_PID1 299
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#define SC_R_M4_1_PID2 300
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#define SC_R_M4_1_PID3 301
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#define SC_R_M4_1_PID4 302
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#define SC_R_M4_1_RGPIO 303
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#define SC_R_M4_1_SEMA42 304
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#define SC_R_M4_1_TPM 305
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#define SC_R_M4_1_PIT 306
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#define SC_R_M4_1_UART 307
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#define SC_R_M4_1_I2C 308
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#define SC_R_M4_1_INTMUX 309
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#define SC_R_M4_1_SIM 310
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#define SC_R_M4_1_WDOG 311
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#define SC_R_M4_1_MU_0B 312
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#define SC_R_M4_1_MU_0A0 313
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#define SC_R_M4_1_MU_0A1 314
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#define SC_R_M4_1_MU_0A2 315
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#define SC_R_M4_1_MU_0A3 316
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#define SC_R_M4_1_MU_1A 317
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#define SC_R_SAI_0 318
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#define SC_R_SAI_1 319
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#define SC_R_SAI_2 320
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#define SC_R_IRQSTR_SCU2 321
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#define SC_R_IRQSTR_DSP 322
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#define SC_R_UNUSED5 323
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#define SC_R_OCRAM 324
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#define SC_R_AUDIO_PLL_0 325
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#define SC_R_PI_0 326
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#define SC_R_PI_0_PWM_0 327
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#define SC_R_PI_0_PWM_1 328
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#define SC_R_PI_0_I2C_0 329
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#define SC_R_PI_0_PLL 330
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#define SC_R_PI_1 331
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#define SC_R_PI_1_PWM_0 332
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#define SC_R_PI_1_PWM_1 333
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#define SC_R_PI_1_I2C_0 334
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#define SC_R_PI_1_PLL 335
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#define SC_R_SC_PID0 336
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#define SC_R_SC_PID1 337
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#define SC_R_SC_PID2 338
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#define SC_R_SC_PID3 339
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#define SC_R_SC_PID4 340
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#define SC_R_SC_SEMA42 341
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#define SC_R_SC_TPM 342
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#define SC_R_SC_PIT 343
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#define SC_R_SC_UART 344
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#define SC_R_SC_I2C 345
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#define SC_R_SC_MU_0B 346
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#define SC_R_SC_MU_0A0 347
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#define SC_R_SC_MU_0A1 348
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#define SC_R_SC_MU_0A2 349
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#define SC_R_SC_MU_0A3 350
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#define SC_R_SC_MU_1A 351
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#define SC_R_SYSCNT_RD 352
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#define SC_R_SYSCNT_CMP 353
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#define SC_R_DEBUG 354
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#define SC_R_SYSTEM 355
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#define SC_R_SNVS 356
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#define SC_R_OTP 357
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#define SC_R_VPU_PID0 358
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#define SC_R_VPU_PID1 359
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#define SC_R_VPU_PID2 360
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#define SC_R_VPU_PID3 361
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#define SC_R_VPU_PID4 362
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#define SC_R_VPU_PID5 363
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#define SC_R_VPU_PID6 364
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#define SC_R_VPU_PID7 365
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#define SC_R_VPU_UART 366
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#define SC_R_VPUCORE 367
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#define SC_R_VPUCORE_0 368
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#define SC_R_VPUCORE_1 369
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#define SC_R_VPUCORE_2 370
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#define SC_R_VPUCORE_3 371
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#define SC_R_DMA_4_CH0 372
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#define SC_R_DMA_4_CH1 373
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#define SC_R_DMA_4_CH2 374
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#define SC_R_DMA_4_CH3 375
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#define SC_R_DMA_4_CH4 376
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#define SC_R_ISI_CH0 377
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#define SC_R_ISI_CH1 378
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#define SC_R_ISI_CH2 379
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#define SC_R_ISI_CH3 380
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#define SC_R_ISI_CH4 381
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#define SC_R_ISI_CH5 382
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#define SC_R_ISI_CH6 383
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#define SC_R_ISI_CH7 384
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#define SC_R_MJPEG_DEC_S0 385
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#define SC_R_MJPEG_DEC_S1 386
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#define SC_R_MJPEG_DEC_S2 387
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#define SC_R_MJPEG_DEC_S3 388
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#define SC_R_MJPEG_ENC_S0 389
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#define SC_R_MJPEG_ENC_S1 390
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#define SC_R_MJPEG_ENC_S2 391
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#define SC_R_MJPEG_ENC_S3 392
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#define SC_R_MIPI_0 393
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#define SC_R_MIPI_0_PWM_0 394
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#define SC_R_MIPI_0_I2C_0 395
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#define SC_R_MIPI_0_I2C_1 396
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#define SC_R_MIPI_1 397
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#define SC_R_MIPI_1_PWM_0 398
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#define SC_R_MIPI_1_I2C_0 399
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#define SC_R_MIPI_1_I2C_1 400
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#define SC_R_CSI_0 401
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#define SC_R_CSI_0_PWM_0 402
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#define SC_R_CSI_0_I2C_0 403
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#define SC_R_CSI_1 404
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#define SC_R_CSI_1_PWM_0 405
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#define SC_R_CSI_1_I2C_0 406
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#define SC_R_HDMI 407
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#define SC_R_HDMI_I2S 408
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#define SC_R_HDMI_I2C_0 409
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#define SC_R_HDMI_PLL_0 410
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#define SC_R_HDMI_RX 411
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#define SC_R_HDMI_RX_BYPASS 412
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#define SC_R_HDMI_RX_I2C_0 413
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#define SC_R_ASRC_0 414
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#define SC_R_ESAI_0 415
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#define SC_R_SPDIF_0 416
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#define SC_R_SPDIF_1 417
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#define SC_R_SAI_3 418
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#define SC_R_SAI_4 419
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#define SC_R_SAI_5 420
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#define SC_R_GPT_5 421
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#define SC_R_GPT_6 422
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#define SC_R_GPT_7 423
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#define SC_R_GPT_8 424
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#define SC_R_GPT_9 425
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#define SC_R_GPT_10 426
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#define SC_R_DMA_2_CH5 427
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#define SC_R_DMA_2_CH6 428
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#define SC_R_DMA_2_CH7 429
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#define SC_R_DMA_2_CH8 430
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#define SC_R_DMA_2_CH9 431
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#define SC_R_DMA_2_CH10 432
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#define SC_R_DMA_2_CH11 433
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#define SC_R_DMA_2_CH12 434
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#define SC_R_DMA_2_CH13 435
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#define SC_R_DMA_2_CH14 436
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#define SC_R_DMA_2_CH15 437
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#define SC_R_DMA_2_CH16 438
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#define SC_R_DMA_2_CH17 439
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#define SC_R_DMA_2_CH18 440
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#define SC_R_DMA_2_CH19 441
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#define SC_R_DMA_2_CH20 442
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#define SC_R_DMA_2_CH21 443
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#define SC_R_DMA_2_CH22 444
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#define SC_R_DMA_2_CH23 445
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#define SC_R_DMA_2_CH24 446
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#define SC_R_DMA_2_CH25 447
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#define SC_R_DMA_2_CH26 448
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#define SC_R_DMA_2_CH27 449
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#define SC_R_DMA_2_CH28 450
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#define SC_R_DMA_2_CH29 451
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#define SC_R_DMA_2_CH30 452
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#define SC_R_DMA_2_CH31 453
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#define SC_R_ASRC_1 454
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#define SC_R_ESAI_1 455
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#define SC_R_SAI_6 456
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#define SC_R_SAI_7 457
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#define SC_R_AMIX 458
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#define SC_R_MQS_0 459
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#define SC_R_DMA_3_CH0 460
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#define SC_R_DMA_3_CH1 461
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#define SC_R_DMA_3_CH2 462
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#define SC_R_DMA_3_CH3 463
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#define SC_R_DMA_3_CH4 464
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#define SC_R_DMA_3_CH5 465
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#define SC_R_DMA_3_CH6 466
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#define SC_R_DMA_3_CH7 467
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#define SC_R_DMA_3_CH8 468
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#define SC_R_DMA_3_CH9 469
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#define SC_R_DMA_3_CH10 470
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#define SC_R_DMA_3_CH11 471
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#define SC_R_DMA_3_CH12 472
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#define SC_R_DMA_3_CH13 473
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#define SC_R_DMA_3_CH14 474
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#define SC_R_DMA_3_CH15 475
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#define SC_R_DMA_3_CH16 476
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#define SC_R_DMA_3_CH17 477
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#define SC_R_DMA_3_CH18 478
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#define SC_R_DMA_3_CH19 479
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#define SC_R_DMA_3_CH20 480
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#define SC_R_DMA_3_CH21 481
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#define SC_R_DMA_3_CH22 482
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#define SC_R_DMA_3_CH23 483
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#define SC_R_DMA_3_CH24 484
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#define SC_R_DMA_3_CH25 485
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#define SC_R_DMA_3_CH26 486
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#define SC_R_DMA_3_CH27 487
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#define SC_R_DMA_3_CH28 488
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#define SC_R_DMA_3_CH29 489
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#define SC_R_DMA_3_CH30 490
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#define SC_R_DMA_3_CH31 491
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#define SC_R_AUDIO_PLL_1 492
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#define SC_R_AUDIO_CLK_0 493
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#define SC_R_AUDIO_CLK_1 494
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#define SC_R_MCLK_OUT_0 495
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#define SC_R_MCLK_OUT_1 496
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#define SC_R_PMIC_0 497
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#define SC_R_PMIC_1 498
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#define SC_R_SECO 499
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#define SC_R_CAAM_JR1 500
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#define SC_R_CAAM_JR2 501
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#define SC_R_CAAM_JR3 502
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#define SC_R_SECO_MU_2 503
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#define SC_R_SECO_MU_3 504
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#define SC_R_SECO_MU_4 505
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#define SC_R_HDMI_RX_PWM_0 506
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#define SC_R_A35 507
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#define SC_R_A35_0 508
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#define SC_R_A35_1 509
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#define SC_R_A35_2 510
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#define SC_R_A35_3 511
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#define SC_R_DSP 512
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#define SC_R_DSP_RAM 513
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#define SC_R_CAAM_JR1_OUT 514
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#define SC_R_CAAM_JR2_OUT 515
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#define SC_R_CAAM_JR3_OUT 516
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#define SC_R_VPU_DEC_0 517
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#define SC_R_VPU_ENC_0 518
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#define SC_R_CAAM_JR0 519
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#define SC_R_CAAM_JR0_OUT 520
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#define SC_R_PMIC_2 521
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#define SC_R_DBLOGIC 522
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#define SC_R_HDMI_PLL_1 523
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#define SC_R_BOARD_R0 524
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#define SC_R_BOARD_R1 525
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#define SC_R_BOARD_R2 526
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#define SC_R_BOARD_R3 527
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#define SC_R_BOARD_R4 528
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#define SC_R_BOARD_R5 529
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#define SC_R_BOARD_R6 530
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#define SC_R_BOARD_R7 531
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#define SC_R_MJPEG_DEC_MP 532
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#define SC_R_MJPEG_ENC_MP 533
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#define SC_R_VPU_TS_0 534
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#define SC_R_VPU_MU_0 535
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#define SC_R_VPU_MU_1 536
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#define SC_R_VPU_MU_2 537
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#define SC_R_VPU_MU_3 538
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#define SC_R_VPU_ENC_1 539
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#define SC_R_VPU 540
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#define SC_R_LAST 541
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#define SC_R_NONE 0xFFF0
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#endif /* DT_BINDINGS_RSCRC_IMX_H */
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