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https://github.com/AsahiLinux/u-boot
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4bc0104c97
This patch adds support for MediaTek MT7621 SoC. All files are dedicated for u-boot. The default build target is u-boot-mt7621.bin. The specification of this chip: https://www.mediatek.com/products/homenetworking/mt7621 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
349 lines
6.1 KiB
Text
349 lines
6.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <dt-bindings/clock/mt7621-clk.h>
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#include <dt-bindings/reset/mt7621-reset.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7621-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "mips,mips1004Kc";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "mips,mips1004Kc";
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reg = <1>;
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};
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};
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clk48m: clk48m {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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clk50m: clk50m {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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sysc: sysctrl@1e000000 {
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compatible = "mediatek,mt7621-sysc", "syscon";
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reg = <0x1e000000 0x100>;
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clkctrl: clock-controller@1e000030 {
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compatible = "mediatek,mt7621-clk";
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mediatek,memc = <&memc>;
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#clock-cells = <1>;
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};
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};
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rstctrl: reset-controller@1e000034 {
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compatible = "mediatek,mtmips-reset";
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reg = <0x1e000034 0x4>;
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#reset-cells = <1>;
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};
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reboot: resetctl-reboot {
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compatible = "resetctl-reboot";
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resets = <&rstctrl RST_SYS>;
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reset-names = "sysreset";
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};
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memc: memctrl@1e005000 {
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compatible = "mediatek,mt7621-memc", "syscon";
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reg = <0x1e005000 0x1000>;
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};
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pinctrl: pinctrl@1e000060 {
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compatible = "mediatek,mt7621-pinctrl";
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reg = <0x1e000048 0x30>;
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pin_state {
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};
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uart1_pins: uart1_pins {
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groups = "uart1";
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function = "uart";
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};
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uart2_pins: uart2_pins {
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groups = "uart2";
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function = "uart";
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};
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uart3_pins: uart3_pins {
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groups = "uart3";
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function = "uart";
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};
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sdxc_pins: sdxc_pins {
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groups = "sdxc";
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function = "sdxc";
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};
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spi_pins: spi_pins {
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groups = "spi";
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function = "spi";
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};
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eth_pins: eth_pins {
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mdio_pins {
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groups = "mdio";
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function = "mdio";
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};
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rgmii1_pins {
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groups = "rgmii1";
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function = "rgmii";
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};
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esw_pins {
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groups = "esw int";
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function = "esw int";
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};
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mdio_pconf {
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groups = "mdio";
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drive-strength = <2>;
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};
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};
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};
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watchdog: watchdog@1e000100 {
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compatible = "mediatek,mt7621-wdt";
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reg = <0x1e000100 0x40>;
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resets = <&rstctrl RST_TIMER>;
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reset-names = "wdt";
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status = "disabled";
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};
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gpio: gpio@1e000600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mtk,mt7621-gpio";
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reg = <0x1e000600 0x100>;
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resets = <&rstctrl RST_PIO>;
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reset-names = "pio";
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gpio0: bank@0 {
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reg = <0>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: bank@1 {
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reg = <1>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: bank@2 {
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reg = <2>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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spi: spi@1e000b00 {
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compatible = "ralink,mt7621-spi";
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reg = <0x1e000b00 0x40>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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resets = <&rstctrl RST_SPI>;
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reset-names = "spi";
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clocks = <&clkctrl MT7621_CLK_SPI>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: uart1@1e000c00 {
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compatible = "mediatek,hsuart", "ns16550a";
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reg = <0x1e000c00 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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clocks = <&clkctrl MT7621_CLK_UART1>;
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resets = <&rstctrl RST_UART1>;
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reg-shift = <2>;
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};
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uart1: uart2@1e000d00 {
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compatible = "mediatek,hsuart", "ns16550a";
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reg = <0x1e000d00 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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clocks = <&clkctrl MT7621_CLK_UART2>;
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resets = <&rstctrl RST_UART2>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: uart3@1e000e00 {
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compatible = "mediatek,hsuart", "ns16550a";
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reg = <0x1e000e00 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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clocks = <&clkctrl MT7621_CLK_UART3>;
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resets = <&rstctrl RST_UART3>;
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reg-shift = <2>;
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status = "disabled";
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};
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eth: eth@1e100000 {
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compatible = "mediatek,mt7621-eth";
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reg = <0x1e100000 0x20000>;
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mediatek,ethsys = <&sysc>;
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pinctrl-names = "default";
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pinctrl-0 = <ð_pins>;
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resets = <&rstctrl RST_FE>, <&rstctrl RST_GMAC>, <&rstctrl RST_MCM>;
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reset-names = "fe", "gmac", "mcm";
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clocks = <&clkctrl MT7621_CLK_GDMA>,
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<&clkctrl MT7621_CLK_ETH>;
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clock-names = "gmac", "fe";
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#address-cells = <1>;
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#size-cells = <0>;
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mediatek,gmac-id = <0>;
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phy-mode = "rgmii";
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mediatek,switch = "mt7530";
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mediatek,mcm;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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mmc: mmc@1e130000 {
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compatible = "mediatek,mt7621-mmc";
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reg = <0x1e130000 0x4000>;
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status = "disabled";
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bus-width = <4>;
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builtin-cd = <1>;
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r_smpl = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdxc_pins>;
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clocks = <&clk50m>, <&clkctrl MT7621_CLK_SHXC>;
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clock-names = "source", "hclk";
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resets = <&rstctrl RST_SDXC>;
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};
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ssusb: usb@1e1c0000 {
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compatible = "mediatek,mt7621-xhci", "mediatek,mtk-xhci";
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reg = <0x1e1c0000 0x1000>, <0x1e1d0700 0x100>;
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reg-names = "mac", "ippc";
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clocks = <&clk48m>, <&clk48m>;
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clock-names = "sys_ck", "ref_ck";
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phys = <&u2port0 PHY_TYPE_USB2>,
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<&u3port0 PHY_TYPE_USB3>,
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<&u2port1 PHY_TYPE_USB2>;
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status = "disabled";
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};
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u3phy: usb-phy@1e1d0000 {
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compatible = "mediatek,mt7621-u3phy",
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"mediatek,generic-tphy-v1";
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reg = <0x1e1d0000 0x700>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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u2port0: usb-phy@1e1d0800 {
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reg = <0x1e1d0800 0x0100>;
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#phy-cells = <1>;
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clocks = <&clk48m>;
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clock-names = "ref";
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};
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u3port0: usb-phy@1e1d0900 {
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reg = <0x1e1d0900 0x0100>;
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#phy-cells = <1>;
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};
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u2port1: usb-phy@1e1d1000 {
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reg = <0x1e1d1000 0x0100>;
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#phy-cells = <1>;
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clocks = <&clk48m>;
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clock-names = "ref";
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};
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};
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i2c: i2c@1e000900 {
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compatible = "i2c-gpio";
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status = "disabled";
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i2c-gpio,delay-us = <3>;
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gpios = <&gpio0 3 1>, /* PIN3 as SDA */
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<&gpio0 4 1>; /* PIN4 as CLK */
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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