mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-25 04:23:46 +00:00
70f24fa02b
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16 SoCs and all existing boards from the Linux v5.18-rc1 tag. These changes are combined into one commit due to interdependencies: - The unit addresses were removed from bitbanged I2C buses, which drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts and sun6i-a31-colombus.dts. - The pinctrl nodes were renamed, including some used by the shared header sunxi-reference-design-tablet.dtsi. To maintain ABI compatibility with existing LTS kernels, one change moving some IP blocks to the r_intc interrupt controller is excluded. This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2. This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree. This commit also adds the following new board devicetrees: - sun5i-a13-licheepi-one.dts - sun5i-a13-pocketbook-touch-lux-3.dts - sun5i-gr8-evb.dts - sun8i-a23-ippo-q8h-v1.2.dts - sun8i-a23-ippo-q8h-v5.dts - sun8i-a33-et-q8-v1.6.dts - sun8i-a33-ippo-q8h-v1.2.dts - sun8i-r16-nintendo-super-nes-classic.dts As with the other SoCs, updates of note are conversion of GPIO pull-up from pinconf to GPIO flags and renaming the detection GPIO properties in the USB PHY nodes. Signed-off-by: Samuel Holland <samuel@sholland.org>
58 lines
776 B
Text
58 lines
776 B
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
|
|
*
|
|
* Minimal dts file for the Mixtile LOFT-Q for u-boot only
|
|
*/
|
|
|
|
/dts-v1/;
|
|
#include "sun6i-a31.dtsi"
|
|
|
|
/ {
|
|
model = "Mixtile LOFT-Q";
|
|
compatible = "mixtile,loft-q", "allwinner,sun6i-a31";
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
};
|
|
|
|
&ehci0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&ehci1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gmac {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&gmac_rgmii_pins>;
|
|
phy = <&phy1>;
|
|
phy-mode = "rgmii";
|
|
status = "okay";
|
|
};
|
|
|
|
&mdio {
|
|
phy1: ethernet-phy@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
&ohci0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&ohci1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_ph_pins>;
|
|
status = "okay";
|
|
};
|