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fdf8f29dc7
BCM68360 is a variant within the BCM6856 chip family. Now that BCM6856
is supported under CONFIG_ARCH_BCMBCA and CONFIG_BCM6856, remove the
original ARCH_BCM68360 support and migrate its configuration and dts
settings. This includes:
- Remove the bcm968360bg board folder. It is replaced by the generic
bcmbca board folder.
- Merge the 68360.dtsi setting to the new 6856.dtsi file. Update board
dts with the new compatible string.
- Merge broadcom_bcm968360bg.h setting to the new bcm96856.h file.
- Remove bcm968360bg_ram_defconfig as a basic config version of
bcm96856_defconfig is now added.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
253 lines
5.1 KiB
Text
253 lines
5.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
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* Copyright 2022 Broadcom Ltd.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "brcm,bcm6856", "brcm,bcmbca";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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B53_0: cpu@0 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_1: cpu@1 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x1>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&B53_0>, <&B53_1>;
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};
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clocks: clocks {
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u-boot,dm-pre-reloc;
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periph_clk:periph-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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hsspi_pll: hsspi-pll {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&periph_clk>;
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clock-mult = <2>;
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clock-div = <1>;
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};
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wdt_clk: wdt-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&periph_clk>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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axi@81000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x81000000 0x8000>;
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gic: interrupt-controller@1000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1000 0x1000>, /* GICD */
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<0x2000 0x2000>, /* GICC */
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<0x4000 0x2000>, /* GICH */
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<0x6000 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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};
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bus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0xff800000 0x800000>;
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u-boot,dm-pre-reloc;
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uart0: serial@640 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x640 0x18>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "disabled";
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};
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wdt1: watchdog@480 {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x480 0x14>;
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clocks = <&wdt_clk>;
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};
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wdt2: watchdog@4c0 {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x4c0 0x14>;
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clocks = <&wdt_clk>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdt1>;
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};
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leds: led-controller@800 {
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compatible = "brcm,bcm6858-leds";
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reg = <0x800 0xe4>;
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status = "disabled";
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};
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gpio0: gpio-controller@500 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x500 0x4>,
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<0x520 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio-controller@504 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x504 0x4>,
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<0x524 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio2: gpio-controller@508 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x508 0x4>,
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<0x528 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio3: gpio-controller@50c {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x50c 0x4>,
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<0x52c 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio4: gpio-controller@510 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x510 0x4>,
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<0x530 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio5: gpio-controller@514 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x514 0x4>,
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<0x534 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio6: gpio-controller@518 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x518 0x4>,
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<0x538 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio7: gpio-controller@51c {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x51c 0x4>,
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<0x53c 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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hsspi: spi-controller@1000 {
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compatible = "brcm,bcm6328-hsspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1000 0x600>;
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clocks = <&hsspi_pll>, <&hsspi_pll>;
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clock-names = "hsspi", "pll";
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spi-max-frequency = <100000000>;
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num-cs = <8>;
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status = "disabled";
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};
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nand: nand-controller@1800 {
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compatible = "brcm,nand-bcm68360",
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"brcm,brcmnand-v5.0",
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"brcm,brcmnand";
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reg-names = "nand", "nand-int-base", "nand-cache";
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reg = <0x1800 0x180>,
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<0x2000 0x10>,
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<0x1c00 0x200>;
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parameter-page-big-endian = <0>;
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status = "disabled";
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};
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};
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};
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