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22c9de064a
For 64B cacheline SoC, set the fixed 8-beat burst len, for 32B cacheline SoC, set the On-The-Fly as default. Signed-off-by: Dave Liu <daveliu@freescale.com> |
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.. | ||
common_timing_params.h | ||
ctrl_regs.c | ||
ddr.h | ||
ddr1_dimm_params.c | ||
ddr2_dimm_params.c | ||
ddr3_dimm_params.c | ||
lc_common_dimm_params.c | ||
main.c | ||
Makefile | ||
options.c | ||
util.c |