mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 05:42:58 +00:00
24a7a3c1c0
Synchronise device tree with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
239 lines
5.1 KiB
Text
239 lines
5.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2020 Gateworks Corporation
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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/ {
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aliases {
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usb0 = &usbotg1;
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usb1 = &usbotg2;
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};
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led-controller {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led-0 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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pps {
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compatible = "pps-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pps>;
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gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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reg_usb_otg1_vbus: regulator-usb-otg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usb1_en>;
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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};
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/* off-board header */
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&gpio1 {
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gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",
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"", "dio1", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&gpio4 {
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gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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accelerometer@19 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_accel>;
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compatible = "st,lis2de12";
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reg = <0x19>;
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st,drdy-int-pin = <1>;
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interrupt-parent = <&gpio4>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "INT1";
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};
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};
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/* off-board header */
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&pcie_phy {
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
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fsl,clkreq-unsupported;
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clocks = <&pcie0_refclk>;
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clock-names = "ref";
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status = "okay";
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
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<&pcie0_refclk>;
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clock-names = "pcie", "pcie_aux", "pcie_bus";
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assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
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<&clk IMX8MM_CLK_PCIE1_CTRL>;
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assigned-clock-rates = <10000000>, <250000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
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<&clk IMX8MM_SYS_PLL2_250M>;
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status = "okay";
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};
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/* GPS */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* off-board header */
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "otg";
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over-current-active-low;
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
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MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
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MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
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MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
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MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
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MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */
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MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */
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>;
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};
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pinctrl_accel: accelgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
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>;
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};
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pinctrl_gpio_leds: gpioledgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
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MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
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MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
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>;
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
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>;
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};
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pinctrl_pps: ppsgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
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>;
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};
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pinctrl_reg_usb1_en: regusb1grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
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MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
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MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
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>;
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};
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pinctrl_spi2: spi2grp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
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MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
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MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
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MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
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MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
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MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
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>;
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};
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};
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