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a1a34faef2
This patch enables the possibility to set FEC_ENET_ENABLE_TXC_DELAY or FEC_ENET_ENABLE_RXC_DELAY so one can via a define enable the RXC or TXC delay in the MAC. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
332 lines
12 KiB
C
332 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
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* (C) Copyright 2008 Armadeus Systems, nc
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* (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
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* (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
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*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* This file is based on mpc4200fec.h
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* (C) Copyright Motorola, Inc., 2000
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*/
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#ifndef __FEC_MXC_H
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#define __FEC_MXC_H
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#include <clk.h>
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/* Layout description of the FEC */
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struct ethernet_regs {
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/* [10:2]addr = 00 */
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/* Control and status Registers (offset 000-1FF) */
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uint32_t res0[1]; /* MBAR_ETH + 0x000 */
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uint32_t ievent; /* MBAR_ETH + 0x004 */
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uint32_t imask; /* MBAR_ETH + 0x008 */
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uint32_t res1[1]; /* MBAR_ETH + 0x00C */
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uint32_t r_des_active; /* MBAR_ETH + 0x010 */
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uint32_t x_des_active; /* MBAR_ETH + 0x014 */
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uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
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uint32_t ecntrl; /* MBAR_ETH + 0x024 */
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uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
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uint32_t mii_data; /* MBAR_ETH + 0x040 */
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uint32_t mii_speed; /* MBAR_ETH + 0x044 */
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uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */
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uint32_t mib_control; /* MBAR_ETH + 0x064 */
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uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */
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uint32_t r_cntrl; /* MBAR_ETH + 0x084 */
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uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */
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uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */
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uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */
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uint32_t paddr1; /* MBAR_ETH + 0x0E4 */
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uint32_t paddr2; /* MBAR_ETH + 0x0E8 */
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uint32_t op_pause; /* MBAR_ETH + 0x0EC */
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uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */
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uint32_t iaddr1; /* MBAR_ETH + 0x118 */
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uint32_t iaddr2; /* MBAR_ETH + 0x11C */
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uint32_t gaddr1; /* MBAR_ETH + 0x120 */
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uint32_t gaddr2; /* MBAR_ETH + 0x124 */
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uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */
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uint32_t x_wmrk; /* MBAR_ETH + 0x144 */
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uint32_t res10[1]; /* MBAR_ETH + 0x148 */
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uint32_t r_bound; /* MBAR_ETH + 0x14C */
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uint32_t r_fstart; /* MBAR_ETH + 0x150 */
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uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */
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uint32_t erdsr; /* MBAR_ETH + 0x180 */
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uint32_t etdsr; /* MBAR_ETH + 0x184 */
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uint32_t emrbr; /* MBAR_ETH + 0x188 */
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uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */
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/* MIB COUNTERS (Offset 200-2FF) */
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uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */
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uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */
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uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
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uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
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uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */
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uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */
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uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */
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uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */
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uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */
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uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */
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uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */
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uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */
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uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */
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uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */
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uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
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uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
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uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
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uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */
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uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */
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uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
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uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */
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uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */
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uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */
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uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */
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uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */
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uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */
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uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */
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uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */
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uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */
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uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
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uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */
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uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */
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uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */
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uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
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uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
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uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */
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uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */
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uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */
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uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */
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uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */
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uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
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uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */
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uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
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uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
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uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
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uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
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uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
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uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
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uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */
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uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */
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uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
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uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */
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uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */
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uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */
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uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */
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uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
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uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
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#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
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uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
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uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
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uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
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uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */
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uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */
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#else
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uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
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#endif
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};
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#define FEC_IEVENT_HBERR 0x80000000
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#define FEC_IEVENT_BABR 0x40000000
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#define FEC_IEVENT_BABT 0x20000000
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#define FEC_IEVENT_GRA 0x10000000
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#define FEC_IEVENT_TXF 0x08000000
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#define FEC_IEVENT_TXB 0x04000000
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#define FEC_IEVENT_RXF 0x02000000
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#define FEC_IEVENT_RXB 0x01000000
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#define FEC_IEVENT_MII 0x00800000
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#define FEC_IEVENT_EBERR 0x00400000
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#define FEC_IEVENT_LC 0x00200000
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#define FEC_IEVENT_RL 0x00100000
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#define FEC_IEVENT_UN 0x00080000
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#define FEC_IMASK_HBERR 0x80000000
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#define FEC_IMASK_BABR 0x40000000
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#define FEC_IMASKT_BABT 0x20000000
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#define FEC_IMASK_GRA 0x10000000
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#define FEC_IMASKT_TXF 0x08000000
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#define FEC_IMASK_TXB 0x04000000
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#define FEC_IMASKT_RXF 0x02000000
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#define FEC_IMASK_RXB 0x01000000
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#define FEC_IMASK_MII 0x00800000
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#define FEC_IMASK_EBERR 0x00400000
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#define FEC_IMASK_LC 0x00200000
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#define FEC_IMASKT_RL 0x00100000
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#define FEC_IMASK_UN 0x00080000
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#define FEC_RCNTRL_MAX_FL_SHIFT 16
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#define FEC_RCNTRL_LOOP 0x00000001
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#define FEC_RCNTRL_DRT 0x00000002
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#define FEC_RCNTRL_MII_MODE 0x00000004
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#define FEC_RCNTRL_PROM 0x00000008
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#define FEC_RCNTRL_BC_REJ 0x00000010
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#define FEC_RCNTRL_FCE 0x00000020
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#define FEC_RCNTRL_RGMII 0x00000040
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#define FEC_RCNTRL_RMII 0x00000100
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#define FEC_RCNTRL_RMII_10T 0x00000200
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#define FEC_TCNTRL_GTS 0x00000001
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#define FEC_TCNTRL_HBC 0x00000002
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#define FEC_TCNTRL_FDEN 0x00000004
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#define FEC_TCNTRL_TFC_PAUSE 0x00000008
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#define FEC_TCNTRL_RFC_PAUSE 0x00000010
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#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
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#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
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#define FEC_ECNTRL_SPEED 0x00000020
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#define FEC_ECNTRL_DBSWAP 0x00000100
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#define FEC_ECNTRL_TXC_DLY 0x00010000 /* TXC delayed */
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#define FEC_ECNTRL_RXC_DLY 0x00020000 /* RXC delayed */
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#define FEC_X_WMRK_STRFWD 0x00000100
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#define FEC_X_DES_ACTIVE_TDAR 0x01000000
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#define FEC_R_DES_ACTIVE_RDAR 0x01000000
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#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
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/* defines for MIIGSK */
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/* RMII frequency control: 0=50MHz, 1=5MHz */
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#define MIIGSK_CFGR_FRCONT (1 << 6)
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/* loopback mode */
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#define MIIGSK_CFGR_LBMODE (1 << 4)
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/* echo mode */
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#define MIIGSK_CFGR_EMODE (1 << 3)
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/* MII gasket mode field */
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#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
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/* MMI/7-Wire mode */
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#define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
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/* RMII mode */
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#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
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/* reflects MIIGSK Enable bit (RO) */
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#define MIIGSK_ENR_READY (1 << 2)
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/* enable MIGSK (set by default) */
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#define MIIGSK_ENR_EN (1 << 1)
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#endif
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/**
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* @brief Receive & Transmit Buffer Descriptor definitions
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*
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* Note: The first BD must be aligned (see DB_ALIGNMENT)
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*/
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struct fec_bd {
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uint16_t data_length; /* payload's length in bytes */
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uint16_t status; /* BD's staus (see datasheet) */
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uint32_t data_pointer; /* payload's buffer address */
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};
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/* Supported phy types on this platform */
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enum xceiver_type {
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SEVENWIRE, /* 7-wire */
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MII10, /* MII 10Mbps */
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MII100, /* MII 100Mbps */
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RMII, /* RMII */
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RGMII, /* RGMII */
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};
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/* @brief i.MX27-FEC private structure */
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struct fec_priv {
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struct ethernet_regs *eth; /* pointer to register'S base */
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enum xceiver_type xcv_type; /* transceiver type */
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struct fec_bd *rbd_base; /* RBD ring */
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int rbd_index; /* next receive BD to read */
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struct fec_bd *tbd_base; /* TBD ring */
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int tbd_index; /* next transmit BD to write */
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bd_t *bd;
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uint8_t *tdb_ptr;
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int dev_id;
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struct mii_dev *bus;
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#ifdef CONFIG_PHYLIB
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struct phy_device *phydev;
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#else
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int phy_id;
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int (*mii_postcall)(int);
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#endif
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#ifdef CONFIG_DM_REGULATOR
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struct udevice *phy_supply;
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#endif
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#if CONFIG_IS_ENABLED(DM_GPIO)
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struct gpio_desc phy_reset_gpio;
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uint32_t reset_delay;
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uint32_t reset_post_delay;
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#endif
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#ifdef CONFIG_DM_ETH
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u32 interface;
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#endif
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struct clk ipg_clk;
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struct clk ahb_clk;
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struct clk clk_enet_out;
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struct clk clk_ref;
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struct clk clk_ptp;
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u32 clk_rate;
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};
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
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/**
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* @brief Numbers of buffer descriptors for receiving
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*
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* The number defines the stocked memory buffers for the receiving task.
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* Larger values makes no sense in this limited environment.
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*/
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#define FEC_RBD_NUM 64
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/**
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* @brief Define the ethernet packet size limit in memory
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*
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* Note: Do not shrink this number. This will force the FEC to spread larger
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* frames in more than one BD. This is nothing to worry about, but the current
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* driver can't handle it.
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*/
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#define FEC_MAX_PKT_SIZE 1536
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/* Receive BD status bits */
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#define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */
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#define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */
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/* Receive BD status: Buffer is last in frame (useless here!) */
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#define FEC_RBD_LAST 0x0800
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#define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */
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/* Receive BD status: The received frame is broadcast frame */
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#define FEC_RBD_BC 0x0080
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/* Receive BD status: The received frame is multicast frame */
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#define FEC_RBD_MC 0x0040
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#define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */
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#define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */
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#define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */
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#define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */
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#define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */
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#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
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FEC_RBD_OV | FEC_RBD_TR)
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/* Transmit BD status bits */
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#define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */
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#define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */
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#define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */
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#define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */
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#define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */
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/* MII-related definitios */
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#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
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#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
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#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
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#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
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#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
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#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
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#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
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#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
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#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
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#endif /* __FEC_MXC_H */
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