mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-25 12:33:41 +00:00
552a848e4f
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
287 lines
8.5 KiB
C
287 lines
8.5 KiB
C
/*
|
|
* Copyright (C) 2016 Amarula Solutions B.V.
|
|
* Copyright (C) 2016 Engicam S.r.l.
|
|
* Author: Jagan Teki <jagan@amarulasolutions.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <mmc.h>
|
|
|
|
#include <asm/io.h>
|
|
#include <asm/gpio.h>
|
|
#include <linux/sizes.h>
|
|
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/crm_regs.h>
|
|
#include <asm/arch/iomux.h>
|
|
#include <asm/arch/mx6-pins.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
#include <asm/mach-imx/video.h>
|
|
|
|
#include "../common/board.h"
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#ifdef CONFIG_NAND_MXS
|
|
|
|
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
|
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
|
PAD_CTL_SRE_FAST)
|
|
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
|
|
|
iomux_v3_cfg_t gpmi_pads[] = {
|
|
IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
|
|
IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
|
};
|
|
|
|
void setup_gpmi_nand(void)
|
|
{
|
|
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
/* config gpmi nand iomux */
|
|
SETUP_IOMUX_PADS(gpmi_pads);
|
|
|
|
/* gate ENFC_CLK_ROOT clock first,before clk source switch */
|
|
clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
|
|
|
|
/* config gpmi and bch clock to 100 MHz */
|
|
clrsetbits_le32(&mxc_ccm->cs2cdr,
|
|
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
|
|
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
|
|
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
|
|
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
|
|
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
|
|
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
|
|
|
|
/* enable ENFC_CLK_ROOT clock */
|
|
setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
|
|
|
|
/* enable gpmi and bch clock gating */
|
|
setbits_le32(&mxc_ccm->CCGR4,
|
|
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
|
|
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
|
|
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
|
|
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
|
|
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
|
|
|
|
/* enable apbh clock gating */
|
|
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_VIDEO_IPUV3)
|
|
static iomux_v3_cfg_t const rgb_pads[] = {
|
|
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
|
|
IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
|
|
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
|
|
IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
|
|
IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
|
|
IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
|
|
IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
|
|
IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
|
|
IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
|
|
IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
|
|
IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
|
|
IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
|
|
IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
|
|
IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
|
|
IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
|
|
IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
|
|
IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
|
|
IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
|
|
IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
|
|
IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
|
|
IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
|
|
IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
|
|
};
|
|
|
|
static void enable_rgb(struct display_info_t const *dev)
|
|
{
|
|
SETUP_IOMUX_PADS(rgb_pads);
|
|
}
|
|
|
|
struct display_info_t const displays[] = {
|
|
{
|
|
.bus = -1,
|
|
.addr = 0,
|
|
.pixfmt = IPU_PIX_FMT_RGB666,
|
|
.detect = NULL,
|
|
.enable = enable_rgb,
|
|
.mode = {
|
|
.name = "Amp-WD",
|
|
.refresh = 60,
|
|
.xres = 800,
|
|
.yres = 480,
|
|
.pixclock = 30000,
|
|
.left_margin = 30,
|
|
.right_margin = 30,
|
|
.upper_margin = 5,
|
|
.lower_margin = 5,
|
|
.hsync_len = 64,
|
|
.vsync_len = 20,
|
|
.sync = FB_SYNC_EXT,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
}
|
|
},
|
|
};
|
|
|
|
size_t display_count = ARRAY_SIZE(displays);
|
|
|
|
void setup_display(void)
|
|
{
|
|
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
int reg;
|
|
|
|
enable_ipu_clock();
|
|
|
|
/* Turn on LDB0,IPU,IPU DI0 clocks */
|
|
reg = __raw_readl(&mxc_ccm->CCGR3);
|
|
reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
|
|
writel(reg, &mxc_ccm->CCGR3);
|
|
|
|
/* set LDB0, LDB1 clk select to 011/011 */
|
|
reg = readl(&mxc_ccm->cs2cdr);
|
|
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
|
|
MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
|
|
reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
|
|
(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
|
|
writel(reg, &mxc_ccm->cs2cdr);
|
|
|
|
reg = readl(&mxc_ccm->cscmr2);
|
|
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
|
|
writel(reg, &mxc_ccm->cscmr2);
|
|
|
|
reg = readl(&mxc_ccm->chsccdr);
|
|
reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
|
|
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
|
|
writel(reg, &mxc_ccm->chsccdr);
|
|
|
|
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
|
|
IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
|
|
IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
|
|
IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
|
|
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
|
|
IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
|
|
IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
|
|
IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
|
|
IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
|
|
writel(reg, &iomux->gpr[2]);
|
|
|
|
reg = readl(&iomux->gpr[3]);
|
|
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
|
|
(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
|
|
IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
|
|
writel(reg, &iomux->gpr[3]);
|
|
}
|
|
#endif /* CONFIG_VIDEO_IPUV3 */
|
|
|
|
void setenv_fdt_file(void)
|
|
{
|
|
if (is_mx6dq())
|
|
setenv("fdt_file", "imx6q-icore.dtb");
|
|
else if(is_mx6dl() || is_mx6solo())
|
|
setenv("fdt_file", "imx6dl-icore.dtb");
|
|
}
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
/* MMC board initialization is needed till adding DM support in SPL */
|
|
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
|
|
#include <mmc.h>
|
|
#include <fsl_esdhc.h>
|
|
|
|
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
|
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
|
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
|
|
|
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
|
IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
|
|
};
|
|
|
|
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
|
|
|
|
struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
|
{USDHC1_BASE_ADDR, 0, 4},
|
|
};
|
|
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
int ret = 0;
|
|
|
|
switch (cfg->esdhc_base) {
|
|
case USDHC1_BASE_ADDR:
|
|
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
int i, ret;
|
|
|
|
/*
|
|
* According to the board_mmc_init() the following map is done:
|
|
* (U-boot device node) (Physical Port)
|
|
* mmc0 USDHC1
|
|
*/
|
|
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
|
switch (i) {
|
|
case 0:
|
|
SETUP_IOMUX_PADS(usdhc1_pads);
|
|
gpio_direction_input(USDHC1_CD_GPIO);
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
break;
|
|
default:
|
|
printf("Warning - USDHC%d controller not supporting\n",
|
|
i + 1);
|
|
return 0;
|
|
}
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
|
if (ret) {
|
|
printf("Warning: failed to initialize mmc dev %d\n", i);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPL_LOAD_FIT
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
|
|
return 0;
|
|
else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
|
|
return 0;
|
|
else
|
|
return -1;
|
|
}
|
|
#endif
|
|
#endif /* CONFIG_SPL_BUILD */
|