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https://github.com/AsahiLinux/u-boot
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396 lines
11 KiB
ArmAsm
396 lines
11 KiB
ArmAsm
/*
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* Board specific setup info
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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*
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* -- Some bits of code used from rrload's head_OMAP1510.s --
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* Copyright (C) 2002 RidgeRun, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#if defined(CONFIG_OMAP1510)
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#include <./configs/omap1510.h>
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#endif
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#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
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_TEXT_BASE:
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.word TEXT_BASE /* sdram load addr from config.mk */
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Configure 1510 pins functions to match our board.
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*/
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ldr r0, REG_PULL_DWN_CTRL_0
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ldr r1, VAL_PULL_DWN_CTRL_0
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str r1, [r0]
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ldr r0, REG_PULL_DWN_CTRL_1
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ldr r1, VAL_PULL_DWN_CTRL_1
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str r1, [r0]
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ldr r0, REG_PULL_DWN_CTRL_2
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ldr r1, VAL_PULL_DWN_CTRL_2
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str r1, [r0]
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ldr r0, REG_PULL_DWN_CTRL_3
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ldr r1, VAL_PULL_DWN_CTRL_3
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_4
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ldr r1, VAL_FUNC_MUX_CTRL_4
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_5
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ldr r1, VAL_FUNC_MUX_CTRL_5
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_6
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ldr r1, VAL_FUNC_MUX_CTRL_6
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_7
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ldr r1, VAL_FUNC_MUX_CTRL_7
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_8
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ldr r1, VAL_FUNC_MUX_CTRL_8
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_9
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ldr r1, VAL_FUNC_MUX_CTRL_9
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_A
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ldr r1, VAL_FUNC_MUX_CTRL_A
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_B
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ldr r1, VAL_FUNC_MUX_CTRL_B
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_C
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ldr r1, VAL_FUNC_MUX_CTRL_C
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_D
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ldr r1, VAL_FUNC_MUX_CTRL_D
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str r1, [r0]
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ldr r0, REG_VOLTAGE_CTRL_0
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ldr r1, VAL_VOLTAGE_CTRL_0
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str r1, [r0]
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ldr r0, REG_TEST_DBG_CTRL_0
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ldr r1, VAL_TEST_DBG_CTRL_0
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str r1, [r0]
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ldr r0, REG_MOD_CONF_CTRL_0
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ldr r1, VAL_MOD_CONF_CTRL_0
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str r1, [r0]
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/* Move to 1510 mode */
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ldr r0, REG_COMP_MODE_CTRL_0
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ldr r1, VAL_COMP_MODE_CTRL_0
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str r1, [r0]
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/* Set up Traffic Ctlr*/
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ldr r0, REG_TC_IMIF_PRIO
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mov r1, #0x0
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str r1, [r0]
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ldr r0, REG_TC_EMIFS_PRIO
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str r1, [r0]
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ldr r0, REG_TC_EMIFF_PRIO
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str r1, [r0]
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ldr r0, REG_TC_EMIFS_CONFIG
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ldr r1, [r0]
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bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */
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bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */
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str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */
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/* Setup some clock domains */
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ldr r1, =OMAP1510_CLKS
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ldr r0, REG_ARM_IDLECT2
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strh r1, [r0] /* CLKM, Clock domain control. */
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mov r1, #0x01 /* PER_EN bit */
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ldr r0, REG_ARM_RSTCT2
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strh r1, [r0] /* CLKM; Peripheral reset. */
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/* Set CLKM to Sync-Scalable */
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/* I supposidly need to enable the dsp clock before switching */
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mov r1, #0x1000
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ldr r0, REG_ARM_SYSST
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strh r1, [r0]
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mov r0, #0x400
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1:
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subs r0, r0, #0x1 /* wait for any bubbles to finish */
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bne 1b
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ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
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ldr r0, REG_ARM_CKCTL
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strh r1, [r0]
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/* setup DPLL 1 */
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ldr r1, VAL_DPLL1_CTL
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ldr r0, REG_DPLL1_CTL
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strh r1, [r0]
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ands r1, r1, #0x10 /* Check if PLL is enabled. */
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beq lock_end /* Do not look for lock if BYPASS selected */
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2:
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ldrh r1, [r0]
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ands r1, r1, #0x01 /* Check the LOCK bit. */
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beq 2b /* ...loop until bit goes hi. */
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lock_end:
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/* Set memory timings corresponding to the new clock speed */
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/* Check execution location to determine current execution location
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* and branch to appropriate initialization code.
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*/
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mov r0, #0x10000000 /* Load physical SDRAM base. */
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mov r1, pc /* Get current execution location. */
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/* Zero all but top 6 bits of PC, as they alone detect whether an
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* address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
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* valid range for SDRAM on the OMAP 1510/5910.
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*/
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and r1, r1, #0xfc000000
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cmp r1, r0 /* Compare. */
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beq skip_sdram /* Skip over EMIF-fast initialization
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* if running from SDRAM.
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*/
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/*
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* Delay for SDRAM initialization.
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*/
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mov r3, #0x1800 /* value should be checked */
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3:
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subs r3, r3, #0x1 /* Decrement count */
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bne 3b
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/*
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* Set SDRAM control values. Disable refresh before MRS command.
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*/
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ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */
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bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
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orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */
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orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */
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ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
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str r3, [r2] /* Store the passed value with AR disabled. */
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ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */
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ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */
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str r1, [r2] /* Store the passed value.*/
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ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
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str r0, [r2] /* Store the passed value. */
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/*
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* Delay for SDRAM initialization.
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*/
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mov r3, #0x1800
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4:
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subs r3, r3, #1 /* Decrement count. */
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bne 4b
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skip_sdram:
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/* slow interface */
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ldr r1, VAL_TC_EMIFS_CS0_CONFIG
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ldr r0, REG_TC_EMIFS_CS0_CONFIG
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str r1, [r0] /* Chip Select 0 */
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ldr r1, VAL_TC_EMIFS_CS1_CONFIG
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ldr r0, REG_TC_EMIFS_CS1_CONFIG
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str r1, [r0] /* Chip Select 1 */
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ldr r1, VAL_TC_EMIFS_CS2_CONFIG
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ldr r0, REG_TC_EMIFS_CS2_CONFIG
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str r1, [r0] /* Chip Select 2 */
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ldr r1, VAL_TC_EMIFS_CS3_CONFIG
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ldr r0, REG_TC_EMIFS_CS3_CONFIG
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str r1, [r0] /* Chip Select 3 */
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/* Next, Enable the RS232 Line Drivers in the FPGA. */
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/* Also, power on the audio CODEC's amplifier here, */
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/* which will make a noise on the audio output. */
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/* This is done here instead of in the kernel so there */
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/* isn't a loud popping noise at the start of each */
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/* song. */
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/* Also, disable the CODEC's clocks. */
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/* omap1510-HelenP1 [specific] */
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ldr r0, REG_FPGA_POWER
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mov r1, #0
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ldr r2, REG_FPGA_DIP_SWITCH
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ldrb r3, [r2]
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cmp r3, #0x8
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movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */
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strb r1, [r0]
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ldr r0, REG_FPGA_AUDIO
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mov r1, #0x0 /* Disable sound driver (CODEC clocks) */
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strb r1, [r0]
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/* back to arch calling code */
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mov pc, lr
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/* the literal pools origin */
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.ltorg
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/* OMAP configuration registers */
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REG_FUNC_MUX_CTRL_0: /* 32 bits */
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.word 0xfffe1000
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REG_FUNC_MUX_CTRL_1: /* 32 bits */
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.word 0xfffe1004
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REG_FUNC_MUX_CTRL_2: /* 32 bits */
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.word 0xfffe1008
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REG_COMP_MODE_CTRL_0: /* 32 bits */
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.word 0xfffe100c
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REG_FUNC_MUX_CTRL_3: /* 32 bits */
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.word 0xfffe1010
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REG_FUNC_MUX_CTRL_4: /* 32 bits */
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.word 0xfffe1014
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REG_FUNC_MUX_CTRL_5: /* 32 bits */
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.word 0xfffe1018
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REG_FUNC_MUX_CTRL_6: /* 32 bits */
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.word 0xfffe101c
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REG_FUNC_MUX_CTRL_7: /* 32 bits */
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.word 0xfffe1020
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REG_FUNC_MUX_CTRL_8: /* 32 bits */
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.word 0xfffe1024
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REG_FUNC_MUX_CTRL_9: /* 32 bits */
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.word 0xfffe1028
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REG_FUNC_MUX_CTRL_A: /* 32 bits */
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.word 0xfffe102C
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REG_FUNC_MUX_CTRL_B: /* 32 bits */
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.word 0xfffe1030
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REG_FUNC_MUX_CTRL_C: /* 32 bits */
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.word 0xfffe1034
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REG_FUNC_MUX_CTRL_D: /* 32 bits */
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.word 0xfffe1038
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REG_PULL_DWN_CTRL_0: /* 32 bits */
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.word 0xfffe1040
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REG_PULL_DWN_CTRL_1: /* 32 bits */
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.word 0xfffe1044
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REG_PULL_DWN_CTRL_2: /* 32 bits */
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.word 0xfffe1048
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REG_PULL_DWN_CTRL_3: /* 32 bits */
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.word 0xfffe104c
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REG_VOLTAGE_CTRL_0: /* 32 bits */
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.word 0xfffe1060
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REG_TEST_DBG_CTRL_0: /* 32 bits */
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.word 0xfffe1070
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REG_MOD_CONF_CTRL_0: /* 32 bits */
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.word 0xfffe1080
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REG_TC_IMIF_PRIO: /* 32 bits */
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.word 0xfffecc00
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REG_TC_EMIFS_PRIO: /* 32 bits */
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.word 0xfffecc04
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REG_TC_EMIFF_PRIO: /* 32 bits */
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.word 0xfffecc08
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REG_TC_EMIFS_CONFIG: /* 32 bits */
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.word 0xfffecc0c
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REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
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.word 0xfffecc10
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REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
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.word 0xfffecc14
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REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
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.word 0xfffecc18
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REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
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.word 0xfffecc1c
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REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */
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.word 0xfffecc20
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REG_TC_EMIFF_MRS: /* 32 bits */
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.word 0xfffecc24
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/* MPU clock/reset/power mode control registers */
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REG_ARM_CKCTL: /* 16 bits */
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.word 0xfffece00
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REG_ARM_IDLECT2: /* 16 bits */
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.word 0xfffece08
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REG_ARM_RSTCT2: /* 16 bits */
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.word 0xfffece14
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REG_ARM_SYSST: /* 16 bits */
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.word 0xfffece18
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/* DPLL control registers */
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REG_DPLL1_CTL: /* 16 bits */
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.word 0xfffecf00
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/* identification code register */
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REG_IDCODE: /* 32 bits */
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.word 0xfffed404
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/* Innovator specific */
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REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */
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.word 0x08000003
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REG_FPGA_POWER: /* 8 bits */
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.word 0x08000005
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REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */
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.word 0x0800000c
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REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */
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.word 0x0800000e
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VAL_COMP_MODE_CTRL_0:
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.word 0x0000eaef
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VAL_FUNC_MUX_CTRL_4:
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.word 0x00000000
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VAL_FUNC_MUX_CTRL_5:
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.word 0x00000000
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VAL_FUNC_MUX_CTRL_6:
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.word 0x00000001
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VAL_FUNC_MUX_CTRL_7:
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.word 0x00000000
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VAL_FUNC_MUX_CTRL_8:
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.word 0x10001200
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VAL_FUNC_MUX_CTRL_9:
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.word 0x01201012
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VAL_FUNC_MUX_CTRL_A:
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.word 0x00000248
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VAL_FUNC_MUX_CTRL_B:
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.word 0x00000248
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VAL_FUNC_MUX_CTRL_C:
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.word 0x09000000
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VAL_FUNC_MUX_CTRL_D:
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.word 0x00000000
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VAL_PULL_DWN_CTRL_0:
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.word 0x11a10000
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VAL_PULL_DWN_CTRL_1:
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.word 0x2e047fff
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VAL_PULL_DWN_CTRL_2:
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.word 0xffd603a6
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VAL_PULL_DWN_CTRL_3:
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.word 0x00003e03
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VAL_VOLTAGE_CTRL_0:
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.word 0x00000007
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VAL_TEST_DBG_CTRL_0:
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/* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
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* This slows down internal SRAM accesses.
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*/
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.word 0x00000007
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VAL_MOD_CONF_CTRL_0:
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.word 0x0b000008
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VAL_ARM_CKCTL:
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.word 0x010f
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VAL_DPLL1_CTL:
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.word 0x2710
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VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
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.word 0x00001149
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VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
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.word 0x00004158
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VAL_TC_EMIFS_CS0_CONFIG:
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.word 0x002130b0
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VAL_TC_EMIFS_CS1_CONFIG:
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.word 0x0000f559
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VAL_TC_EMIFS_CS2_CONFIG:
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.word 0x000055f0
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VAL_TC_EMIFS_CS3_CONFIG:
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.word 0x00003331
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VAL_TC_EMIFF_SDRAM_CONFIG:
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.word 0x010290fc
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VAL_TC_EMIFF_MRS:
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.word 0x00000027
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