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https://github.com/AsahiLinux/u-boot
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99c1565082
Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288. Signed-off-by: Simon Glass <sjg@chromium.org>
185 lines
3.3 KiB
C
185 lines
3.3 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* (C) Copyright 2008-2014 Rockchip Electronics
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* Peter, Software Engineering, <superpeter.cai@gmail.com>.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RK3288_H
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#define _ASM_ARCH_CRU_RK3288_H
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#define OSC_HZ (24 * 1000 * 1000)
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#define APLL_HZ (1800 * 1000000)
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#define GPLL_HZ (594 * 1000000)
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#define CPLL_HZ (384 * 1000000)
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#define NPLL_HZ (384 * 1000000)
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/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
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#define PD_BUS_ACLK_HZ 297000000
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#define PD_BUS_HCLK_HZ 148500000
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#define PD_BUS_PCLK_HZ 74250000
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#define PERI_ACLK_HZ 148500000
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#define PERI_HCLK_HZ 148500000
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#define PERI_PCLK_HZ 74250000
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struct rk3288_cru {
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struct rk3288_pll {
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u32 con0;
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u32 con1;
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u32 con2;
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u32 con3;
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} pll[5];
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u32 cru_mode_con;
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u32 reserved0[3];
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u32 cru_clksel_con[43];
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u32 reserved1[21];
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u32 cru_clkgate_con[19];
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u32 reserved2;
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u32 cru_glb_srst_fst_value;
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u32 cru_glb_srst_snd_value;
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u32 cru_softrst_con[12];
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u32 cru_misc_con;
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u32 cru_glb_cnt_th;
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u32 cru_glb_rst_con;
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u32 reserved3;
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u32 cru_glb_rst_st;
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u32 reserved4;
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u32 cru_sdmmc_con[2];
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u32 cru_sdio0_con[2];
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u32 cru_sdio1_con[2];
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u32 cru_emmc_con[2];
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};
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check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
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/* CRU_CLKSEL11_CON */
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enum {
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HSICPHY_DIV_SHIFT = 8,
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HSICPHY_DIV_MASK = 0x3f,
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MMC0_PLL_SHIFT = 6,
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MMC0_PLL_MASK = 3,
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MMC0_PLL_SELECT_CODEC = 0,
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MMC0_PLL_SELECT_GENERAL,
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MMC0_PLL_SELECT_24MHZ,
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MMC0_DIV_SHIFT = 0,
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MMC0_DIV_MASK = 0x3f,
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};
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/* CRU_CLKSEL12_CON */
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enum {
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EMMC_PLL_SHIFT = 0xe,
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EMMC_PLL_MASK = 3,
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EMMC_PLL_SELECT_CODEC = 0,
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EMMC_PLL_SELECT_GENERAL,
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EMMC_PLL_SELECT_24MHZ,
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EMMC_DIV_SHIFT = 8,
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EMMC_DIV_MASK = 0x3f,
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SDIO0_PLL_SHIFT = 6,
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SDIO0_PLL_MASK = 3,
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SDIO0_PLL_SELECT_CODEC = 0,
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SDIO0_PLL_SELECT_GENERAL,
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SDIO0_PLL_SELECT_24MHZ,
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SDIO0_DIV_SHIFT = 0,
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SDIO0_DIV_MASK = 0x3f,
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};
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/* CRU_CLKSEL25_CON */
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enum {
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SPI1_PLL_SHIFT = 0xf,
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SPI1_PLL_MASK = 1,
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SPI1_PLL_SELECT_CODEC = 0,
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SPI1_PLL_SELECT_GENERAL,
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SPI1_DIV_SHIFT = 8,
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SPI1_DIV_MASK = 0x7f,
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SPI0_PLL_SHIFT = 7,
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SPI0_PLL_MASK = 1,
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SPI0_PLL_SELECT_CODEC = 0,
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SPI0_PLL_SELECT_GENERAL,
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SPI0_DIV_SHIFT = 0,
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SPI0_DIV_MASK = 0x7f,
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};
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/* CRU_CLKSEL39_CON */
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enum {
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ACLK_HEVC_PLL_SHIFT = 0xe,
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ACLK_HEVC_PLL_MASK = 3,
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ACLK_HEVC_PLL_SELECT_CODEC = 0,
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ACLK_HEVC_PLL_SELECT_GENERAL,
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ACLK_HEVC_PLL_SELECT_NEW,
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ACLK_HEVC_DIV_SHIFT = 8,
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ACLK_HEVC_DIV_MASK = 0x1f,
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SPI2_PLL_SHIFT = 7,
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SPI2_PLL_MASK = 1,
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SPI2_PLL_SELECT_CODEC = 0,
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SPI2_PLL_SELECT_GENERAL,
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SPI2_DIV_SHIFT = 0,
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SPI2_DIV_MASK = 0x7f,
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};
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/* CRU_MODE_CON */
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enum {
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NPLL_WORK_SHIFT = 0xe,
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NPLL_WORK_MASK = 3,
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NPLL_WORK_SLOW = 0,
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NPLL_WORK_NORMAL,
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NPLL_WORK_DEEP,
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GPLL_WORK_SHIFT = 0xc,
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GPLL_WORK_MASK = 3,
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GPLL_WORK_SLOW = 0,
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GPLL_WORK_NORMAL,
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GPLL_WORK_DEEP,
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CPLL_WORK_SHIFT = 8,
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CPLL_WORK_MASK = 3,
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CPLL_WORK_SLOW = 0,
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CPLL_WORK_NORMAL,
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CPLL_WORK_DEEP,
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DPLL_WORK_SHIFT = 4,
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DPLL_WORK_MASK = 3,
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DPLL_WORK_SLOW = 0,
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DPLL_WORK_NORMAL,
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DPLL_WORK_DEEP,
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APLL_WORK_SHIFT = 0,
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APLL_WORK_MASK = 3,
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APLL_WORK_SLOW = 0,
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APLL_WORK_NORMAL,
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APLL_WORK_DEEP,
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};
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/* CRU_APLL_CON0 */
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enum {
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CLKR_SHIFT = 8,
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CLKR_MASK = 0x3f,
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CLKOD_SHIFT = 0,
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CLKOD_MASK = 0xf,
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};
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/* CRU_APLL_CON1 */
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enum {
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LOCK_SHIFT = 0x1f,
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LOCK_MASK = 1,
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LOCK_UNLOCK = 0,
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LOCK_LOCK,
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CLKF_SHIFT = 0,
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CLKF_MASK = 0x1fff,
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};
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#endif
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