mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
1e8f246563
Since commit6239cc8c4e("arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-Boot") ranges have been added to CPSW node which results in U-Boot CPSW driver failing to acquire phy_gmii_sel register range and thus failing to configure GMII mode correctly. Fix this by deleting ranges in -u-boot-dtsi just like its done for other K3 platforms. Fixes:6239cc8c4e("arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-Boot") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
162 lines
1.9 KiB
Text
162 lines
1.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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ethernet0 = &cpsw_port1;
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i2c0 = &wkup_i2c0;
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i2c1 = &mcu_i2c0;
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i2c2 = &mcu_i2c1;
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i2c3 = &main_i2c0;
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};
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};
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&cbass_main {
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u-boot,dm-spl;
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};
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&main_navss {
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u-boot,dm-spl;
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};
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&cbass_mcu_wakeup {
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u-boot,dm-spl;
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timer1: timer@40400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x40400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <25000000>;
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u-boot,dm-spl;
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};
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chipid@43000014 {
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u-boot,dm-spl;
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};
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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};
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&main_pmx0 {
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u-boot,dm-spl;
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};
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&main_uart0 {
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u-boot,dm-spl;
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};
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&mcu_uart0 {
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u-boot,dm-spl;
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};
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&main_sdhci0 {
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u-boot,dm-spl;
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};
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&main_sdhci1 {
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u-boot,dm-spl;
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};
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&wkup_i2c0_pins_default {
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u-boot,dm-spl;
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};
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&wkup_i2c0 {
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u-boot,dm-spl;
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};
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&main_i2c0 {
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u-boot,dm-spl;
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};
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&main_i2c0_pins_default {
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u-boot,dm-spl;
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};
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&exp2 {
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u-boot,dm-spl;
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};
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&mcu_cpsw {
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reg = <0x0 0x46000000 0x0 0x200000>,
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<0x0 0x40f00200 0x0 0x8>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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cpsw-phy-sel@40f04040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg= <0x0 0x40f04040 0x0 0x4>;
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reg-names = "gmii-sel";
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};
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};
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&main_usbss0_pins_default {
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u-boot,dm-spl;
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};
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&usbss0 {
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u-boot,dm-spl;
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ti,usb2-only;
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};
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&usb0 {
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dr_mode = "peripheral";
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u-boot,dm-spl;
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};
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&wkup_gpio_pins_default {
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u-boot,dm-spl;
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};
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&mcu_fss0_hpb0_pins_default {
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u-boot,dm-spl;
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};
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&fss {
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u-boot,dm-spl;
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};
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&hbmc {
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u-boot,dm-spl;
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flash@0,0 {
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u-boot,dm-spl;
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};
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};
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&hbmc_mux {
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u-boot,dm-spl;
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};
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