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System controller revC is using ADI ethernet phy instead of TI because of supply chain issues. Describe reset assert and de-assert times to 10us and 5ms respectively according to the datasheet. Also setup RGMII RX and TX delay values to 2400ps as per board bring up observations. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/2790f6cede7485556d581ab8270dda477fa21522.1695808407.git.michal.simek@amd.com
37 lines
865 B
Text
37 lines
865 B
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP Generic System Controller
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*
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* Copyright (C) 2021 - 2022, Xilinx, Inc.
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* Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include "zynqmp-sc-revB.dts"
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/ {
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model = "ZynqMP Generic System Controller";
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compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp";
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};
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&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */
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/delete-node/ mdio;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@1 { /* ADI1300 */
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#phy-cells = <1>;
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compatible = "ethernet-phy-id0283.bc30";
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reg = <1>;
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adi,rx-internal-delay-ps = <2400>;
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adi,tx-internal-delay-ps = <2400>;
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adi,fifo-depth-bits = <8>;
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reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10>;
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reset-deassert-us = <5000>;
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};
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};
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};
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