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York Sun 36cc0de0b9 armv8: layerscape: Rewrite memory reservation 
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
..
Kconfig NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST 2017-01-24 10:33:59 -05:00
ls1012aqds.c armv8: layerscape: Rewrite memory reservation 2017-03-14 08:44:03 -07:00
ls1012aqds_qixis.h armv8: ls1012a: Add support of ls1012aqds board 2016-06-03 14:12:51 -07:00
MAINTAINERS armv8: ls1012a: Add support of ls1012aqds board 2016-06-03 14:12:51 -07:00
Makefile armv8: ls1012a: Add support of ls1012aqds board 2016-06-03 14:12:51 -07:00
README armv8: ls1012a: Add support of ls1012aqds board 2016-06-03 14:12:51 -07:00

README 

Overview
--------
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
SoC overview.

LS1012AQDS board Overview
-----------------------
 - SERDES Connections, 4 lanes supporting:
      - PCI Express - 3.0
      - SGMII, SGMII 2.5
      - SATA 3.0
 - DDR Controller
     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
 - QSPI Controller
     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
       emulator
 - USB 3.0
    - One USB 3.0 controller with integrated PHY
    - One high-speed USB 3.0 port
 - USB 2.0
    - One USB 2.0 controller with ULPI interface
 - Two enhanced secure digital host controllers:
    - SDHC1 controller can be connected to onboard SDHC connector
    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
 - 2 I2C controllers
 - One SATA onboard connectors
 - UART
 - 5 SAI
    - One SAI port with audio codec SGTL5000:
	• Provides MIC bias
	• Provides headphone and line output
    - One SAI port terminated at 2x6 header
    - Three SAI Tx/Rx ports terminated at 2x3 headers
 - ARM JTAG support

Booting Options
---------------
a) QSPI Flash Emu Boot
b) QSPI Flash 1
c) QSPI Flash 2

QSPI flash map
--------------
Images		| Size	|QSPI Flash Address
------------------------------------------
RCW + PBI	| 1MB	| 0x4000_0000
U-boot 		| 1MB	| 0x4010_0000
U-boot Env 	| 1MB	| 0x4020_0000
PPA FIT image	| 2MB	| 0x4050_0000
Linux ITB	| ~53MB | 0x40A0_0000