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9ae0d55074
This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1. Cc: Frederik Kriewitz <frederik@kriewitz.eu> Signed-off-by: Tom Rini <trini@ti.com>
161 lines
4.3 KiB
C
161 lines
4.3 KiB
C
/*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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* (C) Copyright 2009
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* Frederik Kriewitz <frederik@kriewitz.eu>
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/mach-types.h>
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#include "devkit8000.h"
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#ifdef CONFIG_DRIVER_DM9000
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#include <net.h>
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#include <netdev.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
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#ifdef CONFIG_DRIVER_DM9000
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uchar enetaddr[6];
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u32 die_id_0;
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#endif
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twl4030_power_init();
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#ifdef CONFIG_TWL4030_LED
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twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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/* Configure GPMC registers for DM9000 */
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writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[6].config1);
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writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[6].config2);
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writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[6].config3);
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writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[6].config4);
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writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[6].config5);
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writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[6].config6);
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writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[6].config7);
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/* Use OMAP DIE_ID as MAC address */
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if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
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printf("ethaddr not set, using Die ID\n");
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die_id_0 = readl(&id_base->die_id_0);
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enetaddr[0] = 0x02; /* locally administered */
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enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
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enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
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enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
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enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
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enetaddr[5] = (die_id_0 & 0x000000ff);
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eth_setenv_enetaddr("ethaddr", enetaddr);
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}
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#endif
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_DEVKIT8000();
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}
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(0);
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return 0;
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}
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#endif
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#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
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/*
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* Routine: board_eth_init
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* Description: Setting up the Ethernet hardware.
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*/
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on the first bank. This
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* provides the timing values back to the function that configures
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* the memory. We have either one or two banks of 128MB DDR.
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*/
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void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
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u32 *mr)
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{
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/* General SDRC config */
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*mcfg = MICRON_V_MCFG_165(128 << 20);
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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/* AC timings */
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*ctrla = MICRON_V_ACTIMA_165;
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*ctrlb = MICRON_V_ACTIMB_165;
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*mr = MICRON_V_MR_165;
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}
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