mirror of
https://github.com/AsahiLinux/u-boot
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09f3ca3dd5
We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
334 lines
9.7 KiB
C
334 lines
9.7 KiB
C
/*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_KM83XX_H
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#define __CONFIG_KM83XX_H
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#define CONFIG_DISPLAY_BOARDINFO
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/* include common defines/options for all Keymile boards */
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#include "keymile-common.h"
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#include "km-powerpc.h"
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#ifndef MTDIDS_DEFAULT
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# define MTDIDS_DEFAULT "nor0=boot"
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#endif /* MTDIDS_DEFAULT */
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#ifndef MTDPARTS_DEFAULT
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# define MTDPARTS_DEFAULT "mtdparts=" \
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"boot:" \
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"768k(u-boot)," \
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"128k(env)," \
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"128k(envred)," \
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"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
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#endif /* MTDPARTS_DEFAULT */
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#define CONFIG_MISC_INIT_R
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/*
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* System Clock Setup
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*/
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#define CONFIG_83XX_CLKIN 66000000
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* IMMR new address
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*/
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#define CONFIG_SYS_IMMR 0xE0000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CFG_83XX_DDR_USES_CS0
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/*
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* Manually set up DDR parameters
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*/
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#define CONFIG_DDR_II
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#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_SYS_FLASH_BASE 0xF0000000
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#endif
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/* Reserve 768 kB for Mon */
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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/*
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* Initial RAM Base Address Setup
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/*
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* Init Local Bus Memory Controller:
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*
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* Bank Bus Machine PortSz Size Device
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* ---- --- ------- ------ ----- ------
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* 0 Local GPCM 16 bit 256MB FLASH
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* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
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*
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*/
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
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BR_PS_16 | /* 16 bit port size */ \
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BR_MS_GPCM | /* MSEL = GPCM */ \
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BR_V)
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_5 | \
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OR_GPCM_TRLX_SET | OR_GPCM_EAD)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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/*
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* PRIO1/PIGGY on the local bus CS1
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*/
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
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BR_PS_8 | /* 8 bit port size */ \
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BR_MS_GPCM | /* MSEL = GPCM */ \
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BR_V)
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#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_2 | \
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OR_GPCM_TRLX_SET | OR_GPCM_EAD)
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* Pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_UEC_ETH
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#define CONFIG_ETHPRIME "UEC0"
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#if !defined(CONFIG_MPC8309)
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#define CONFIG_UEC_ETH1 /* GETH1 */
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#define UEC_VERBOSE_DEBUG 1
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#endif
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#ifdef CONFIG_UEC_ETH1
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#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
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#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR 0
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
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#endif
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/*
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* Environment
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#else /* CFG_SYS_RAMBOOT */
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#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
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#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif /* CFG_SYS_RAMBOOT */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_NUM_I2C_BUSES 4
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#define CONFIG_SYS_I2C_MAX_HOPS 1
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 200000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 200000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
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{1, {I2C_NULL_HOP} } }
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#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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#define CONFIG_SYS_DTT_BUS_NUM 1
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_NAND_KMETER1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
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#endif
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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/*
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* Core HID Setup
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*/
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_INSTRUCTION_CACHE)
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#define CONFIG_SYS_HID2 HID2_HBE
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/*
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* MMU Setup
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*/
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR: cache cacheable */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* IMMRBAR & PCI IO: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/* Stack in dcache: cacheable, no memory coherence */
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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/*
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* Internal Definitions
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*/
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#define BOOTFLASH_START 0xF0000000
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#define CONFIG_KM_CONSOLE_TTY "ttyS0"
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_OVERWRITE
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#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
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#define CONFIG_KM_DEF_ENV "km-common=empty\0"
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#endif
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#ifndef CONFIG_KM_DEF_ARCH
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#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_KM_DEF_ENV \
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CONFIG_KM_DEF_ARCH \
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"newenv=" \
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"prot off 0xF00C0000 +0x40000 && " \
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"era 0xF00C0000 +0x40000\0" \
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"unlock=yes\0" \
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""
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#if defined(CONFIG_UEC_ETH)
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#define CONFIG_HAS_ETH0
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#endif
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#endif /* __CONFIG_KM83XX_H */
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