mirror of
https://github.com/AsahiLinux/u-boot
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392 lines
10 KiB
C
392 lines
10 KiB
C
/*
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* (C) Copyright 2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Author: Igor Lisitsin <igor@emcraft.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/*
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* UART test
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*
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* The controllers are configured to loopback mode and several
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* characters are transmitted.
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*/
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#ifdef CONFIG_POST
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#include <post.h>
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#if CONFIG_POST & CFG_POST_UART
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/*
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* This table defines the UART's that should be tested and can
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* be overridden in the board config file
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*/
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#ifndef CFG_POST_UART_TABLE
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#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
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#endif
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#include <asm/processor.h>
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#include <serial.h>
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#if defined(CONFIG_440)
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
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#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
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#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
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#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
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#else
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#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
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#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
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#endif
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
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#endif
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#if defined(CONFIG_440GP)
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#define CR0_MASK 0x3fff0000
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#define CR0_EXTCLK_ENA 0x00600000
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#define CR0_UDIV_POS 16
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#define UDIV_SUBTRACT 1
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#define UART0_SDR cntrl0
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#define MFREG(a, d) d = mfdcr(a)
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#define MTREG(a, d) mtdcr(a, d)
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#else /* #if defined(CONFIG_440GP) */
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/* all other 440 PPC's access clock divider via sdr register */
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#define CR0_MASK 0xdfffffff
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#define CR0_EXTCLK_ENA 0x00800000
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#define CR0_UDIV_POS 0
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#define UDIV_SUBTRACT 0
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#define UART0_SDR sdr_uart0
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#define UART1_SDR sdr_uart1
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#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPe)
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#define UART2_SDR sdr_uart2
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRx)
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#define UART3_SDR sdr_uart3
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#endif
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#define MFREG(a, d) mfsdr(a, d)
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#define MTREG(a, d) mtsdr(a, d)
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#endif /* #if defined(CONFIG_440GP) */
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#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define UCR0_MASK 0x0000007f
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#define UCR1_MASK 0x00007f00
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#define UCR0_UDIV_POS 0
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#define UCR1_UDIV_POS 8
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#define UDIV_MAX 127
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#elif defined(CONFIG_405EX)
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#define UART0_BASE 0xef600200
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#define UART1_BASE 0xef600300
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#define CR0_MASK 0x000000ff
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#define CR0_EXTCLK_ENA 0x00800000
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#define CR0_UDIV_POS 0
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#define UDIV_SUBTRACT 0
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#define UART0_SDR sdr_uart0
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#define UART1_SDR sdr_uart1
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#define MFREG(a, d) mfsdr(a, d)
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#define MTREG(a, d) mtsdr(a, d)
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#else /* CONFIG_405GP || CONFIG_405CR */
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define CR0_MASK 0x00001fff
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#define CR0_EXTCLK_ENA 0x000000c0
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#define CR0_UDIV_POS 1
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#define UDIV_MAX 32
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#endif
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#define UART_RBR 0x00
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#define UART_THR 0x00
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/*
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* Line Status Register.
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*/
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#define asyncLSRDataReady1 0x01
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#define asyncLSROverrunError1 0x02
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#define asyncLSRParityError1 0x04
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#define asyncLSRFramingError1 0x08
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#define asyncLSRBreakInterrupt1 0x10
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#define asyncLSRTxHoldEmpty1 0x20
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#define asyncLSRTxShiftEmpty1 0x40
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#define asyncLSRRxFifoError1 0x80
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_440) || defined(CONFIG_405EX)
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#if !defined(CFG_EXT_SERIAL_CLOCK)
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static void serial_divs (int baudrate, unsigned long *pudiv,
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unsigned short *pbdiv)
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{
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sys_info_t sysinfo;
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unsigned long div; /* total divisor udiv * bdiv */
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unsigned long umin; /* minimum udiv */
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unsigned short diff; /* smallest diff */
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unsigned long udiv; /* best udiv */
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unsigned short idiff; /* current diff */
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unsigned short ibdiv; /* current bdiv */
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unsigned long i;
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unsigned long est; /* current estimate */
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get_sys_info(&sysinfo);
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udiv = 32; /* Assume lowest possible serial clk */
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div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
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umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
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diff = 32; /* highest possible */
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/* i is the test udiv value -- start with the largest
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* possible (32) to minimize serial clock and constrain
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* search to umin.
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*/
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for (i = 32; i > umin; i--) {
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ibdiv = div / i;
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est = i * ibdiv;
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idiff = (est > div) ? (est-div) : (div-est);
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if (idiff == 0) {
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udiv = i;
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break; /* can't do better */
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} else if (idiff < diff) {
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udiv = i; /* best so far */
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diff = idiff; /* update lowest diff*/
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}
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}
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*pudiv = udiv;
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*pbdiv = div / udiv;
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}
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#endif
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static int uart_post_init (unsigned long dev_base)
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{
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unsigned long reg = 0;
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unsigned long udiv;
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unsigned short bdiv;
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volatile char val;
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#ifdef CFG_EXT_SERIAL_CLOCK
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unsigned long tmp;
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#endif
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int i;
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for (i = 0; i < 3500; i++) {
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if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
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break;
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udelay (100);
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}
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MFREG(UART0_SDR, reg);
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reg &= ~CR0_MASK;
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#ifdef CFG_EXT_SERIAL_CLOCK
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reg |= CR0_EXTCLK_ENA;
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udiv = 1;
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tmp = gd->baudrate * 16;
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bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
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#else
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/* For 440, the cpu clock is on divider chain A, UART on divider
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* chain B ... so cpu clock is irrelevant. Get the "optimized"
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* values that are subject to the 1/2 opb clock constraint
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*/
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serial_divs (gd->baudrate, &udiv, &bdiv);
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#endif
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reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
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/*
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* Configure input clock to baudrate generator for all
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* available serial ports here
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*/
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MTREG(UART0_SDR, reg);
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#if defined(UART1_SDR)
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MTREG(UART1_SDR, reg);
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#endif
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#if defined(UART2_SDR)
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MTREG(UART2_SDR, reg);
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#endif
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#if defined(UART3_SDR)
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MTREG(UART3_SDR, reg);
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#endif
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out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
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out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
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out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
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out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
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out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
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out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
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val = in8(dev_base + UART_LSR); /* clear line status */
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val = in8(dev_base + UART_RBR); /* read receive buffer */
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out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
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out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
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return 0;
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}
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#else /* CONFIG_440 */
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static int uart_post_init (unsigned long dev_base)
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{
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unsigned long reg;
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unsigned long tmp;
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unsigned long clk;
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unsigned long udiv;
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unsigned short bdiv;
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volatile char val;
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int i;
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for (i = 0; i < 3500; i++) {
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if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
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break;
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udelay (100);
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}
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#if defined(CONFIG_405EZ)
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serial_divs(gd->baudrate, &udiv, &bdiv);
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clk = tmp = reg = 0;
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#else
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#ifdef CONFIG_405EP
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reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
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clk = gd->cpu_clk;
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tmp = CFG_BASE_BAUD * 16;
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udiv = (clk + tmp / 2) / tmp;
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if (udiv > UDIV_MAX) /* max. n bits for udiv */
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udiv = UDIV_MAX;
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reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
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reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
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mtdcr (cpc0_ucr, reg);
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#else /* CONFIG_405EP */
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reg = mfdcr(cntrl0) & ~CR0_MASK;
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#ifdef CFG_EXT_SERIAL_CLOCK
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clk = CFG_EXT_SERIAL_CLOCK;
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udiv = 1;
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reg |= CR0_EXTCLK_ENA;
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#else
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clk = gd->cpu_clk;
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#ifdef CFG_405_UART_ERRATA_59
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udiv = 31; /* Errata 59: stuck at 31 */
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#else
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tmp = CFG_BASE_BAUD * 16;
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udiv = (clk + tmp / 2) / tmp;
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if (udiv > UDIV_MAX) /* max. n bits for udiv */
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udiv = UDIV_MAX;
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#endif
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#endif
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reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
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mtdcr (cntrl0, reg);
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#endif /* CONFIG_405EP */
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tmp = gd->baudrate * udiv * 16;
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bdiv = (clk + tmp / 2) / tmp;
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#endif /* CONFIG_405EZ */
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out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
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out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
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out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
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out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
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out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
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out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
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val = in8(dev_base + UART_LSR); /* clear line status */
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val = in8(dev_base + UART_RBR); /* read receive buffer */
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out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
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out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
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return (0);
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}
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#endif /* CONFIG_440 */
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static void uart_post_putc (unsigned long dev_base, char c)
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{
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int i;
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out8 (dev_base + UART_THR, c); /* put character out */
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/* Wait for transfer completion */
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for (i = 0; i < 3500; i++) {
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if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
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break;
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udelay (100);
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}
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}
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static int uart_post_getc (unsigned long dev_base)
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{
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int i;
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/* Wait for character available */
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for (i = 0; i < 3500; i++) {
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if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
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break;
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udelay (100);
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}
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return 0xff & in8 (dev_base + UART_RBR);
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}
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static int test_ctlr (unsigned long dev_base, int index)
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{
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int res = -1;
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char test_str[] = "*** UART Test String ***\r\n";
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int i;
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uart_post_init (dev_base);
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for (i = 0; i < sizeof (test_str) - 1; i++) {
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uart_post_putc (dev_base, test_str[i]);
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if (uart_post_getc (dev_base) != test_str[i])
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goto done;
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}
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res = 0;
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done:
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if (res)
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post_log ("uart%d test failed\n", index);
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return res;
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}
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int uart_post_test (int flags)
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{
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int i, res = 0;
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static unsigned long base[] = CFG_POST_UART_TABLE;
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for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
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if (test_ctlr (base[i], i))
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res = -1;
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}
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serial_reinit_all ();
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return res;
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}
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#endif /* CONFIG_POST & CFG_POST_UART */
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#endif /* CONFIG_POST */
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