mirror of
https://github.com/AsahiLinux/u-boot
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267 lines
6.8 KiB
C
267 lines
6.8 KiB
C
/*
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* (C) Copyright 2007
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* Developed for DENX Software Engineering GmbH.
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*
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* Author: Pavel Kolesnikov <concord@emcraft.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* define DEBUG for debugging output (obviously ;-)) */
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <watchdog.h>
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#if defined(CONFIG_POST) && (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
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#include <post.h>
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#if CONFIG_POST & CFG_POST_ECC
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/*
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* MEMORY ECC test
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*
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* This test performs the checks ECC facility of memory.
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*/
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <ppc440.h>
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DECLARE_GLOBAL_DATA_PTR;
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const static unsigned char syndrome_codes[] = {
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0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
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0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
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0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
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0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
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0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
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0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
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0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
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0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
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0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
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};
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#define ECC_START_ADDR 0x10
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#define ECC_STOP_ADDR 0x2000
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#define ECC_PATTERN 0x01010101
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#define ECC_PATTERN_CORR 0x11010101
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#define ECC_PATTERN_UNCORR 0xF1010101
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static int test_ecc_error(void)
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{
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unsigned long value;
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unsigned long hdata, ldata, haddr, laddr;
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unsigned int bit;
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int ret = 0;
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mfsdram(DDR0_23, value);
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for (bit = 0; bit < sizeof(syndrome_codes); bit++)
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if (syndrome_codes[bit] == ((value >> 16) & 0xff))
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break;
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mfsdram(DDR0_00, value);
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if (value & DDR0_00_INT_STATUS_BIT0) {
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debug("Bit0. A single access outside the defined PHYSICAL"
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" memory space detected\n");
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mfsdram(DDR0_32, laddr);
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mfsdram(DDR0_33, haddr);
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debug(" addr = 0x%08x%08x\n", haddr, laddr);
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ret = 1;
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}
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if (value & DDR0_00_INT_STATUS_BIT1) {
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debug("Bit1. Multiple accesses outside the defined PHYSICAL"
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" memory space detected\n");
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ret = 2;
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}
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if (value & DDR0_00_INT_STATUS_BIT2) {
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debug("Bit2. Single correctable ECC event detected\n");
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mfsdram(DDR0_38, laddr);
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mfsdram(DDR0_39, haddr);
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mfsdram(DDR0_40, ldata);
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mfsdram(DDR0_41, hdata);
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debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
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laddr, hdata, ldata, bit);
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ret = 3;
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}
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if (value & DDR0_00_INT_STATUS_BIT3) {
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debug("Bit3. Multiple correctable ECC events detected\n");
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mfsdram(DDR0_38, laddr);
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mfsdram(DDR0_39, haddr);
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mfsdram(DDR0_40, ldata);
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mfsdram(DDR0_41, hdata);
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debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
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laddr, hdata, ldata, bit);
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ret = 4;
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}
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if (value & DDR0_00_INT_STATUS_BIT4) {
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debug("Bit4. Single uncorrectable ECC event detected\n");
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mfsdram(DDR0_34, laddr);
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mfsdram(DDR0_35, haddr);
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mfsdram(DDR0_36, ldata);
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mfsdram(DDR0_37, hdata);
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debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
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laddr, hdata, ldata, bit);
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ret = 5;
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}
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if (value & DDR0_00_INT_STATUS_BIT5) {
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debug("Bit5. Multiple uncorrectable ECC events detected\n");
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mfsdram(DDR0_34, laddr);
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mfsdram(DDR0_35, haddr);
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mfsdram(DDR0_36, ldata);
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mfsdram(DDR0_37, hdata);
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debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
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laddr, hdata, ldata, bit);
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ret = 6;
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}
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if (value & DDR0_00_INT_STATUS_BIT6) {
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debug("Bit6. DRAM initialization complete\n");
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ret = 7;
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}
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/* error status cleared */
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mfsdram(DDR0_00, value);
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mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
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return ret;
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}
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static int test_ecc(unsigned long ecc_addr)
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{
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unsigned long value;
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volatile unsigned *const ecc_mem = (volatile unsigned *) ecc_addr;
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int pret;
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int ret = 0;
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sync();
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eieio();
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WATCHDOG_RESET();
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debug("Entering test_ecc(0x%08lX)\n", ecc_addr);
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out_be32(ecc_mem, ECC_PATTERN);
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out_be32(ecc_mem + 1, ECC_PATTERN);
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in_be32(ecc_mem);
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pret = test_ecc_error();
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if (pret != 0) {
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debug("pret: expected 0, got %d\n", pret);
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ret = 1;
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}
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/* test for correctable error */
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/* disconnect from ecc storage */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_DISABLE);
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/* creating (correctable) single-bit error */
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out_be32(ecc_mem, ECC_PATTERN_CORR);
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/* enable ecc */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_ENABLE);
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sync();
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eieio();
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in_be32(ecc_mem);
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pret = test_ecc_error();
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/* if read data ok, 1 correctable error must be fixed */
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if (pret != 3) {
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debug("pret: expected 3, got %d\n", pret);
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ret = 1;
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}
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/* test for uncorrectable error */
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/* disconnect from ecc storage */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_NO_ECC_RAM);
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/* creating (uncorrectable) multiple-bit error */
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out_be32(ecc_mem, ECC_PATTERN_UNCORR);
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/* enable ecc */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_ENABLE);
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sync();
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eieio();
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in_be32(ecc_mem);
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pret = test_ecc_error();
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/* info about uncorrectable error must appear */
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if (pret != 5) {
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debug("pret: expected 5, got %d\n", pret);
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ret = 1;
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}
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/* remove error from SDRAM */
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out_be32(ecc_mem, ECC_PATTERN);
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/* clear error caused by read-modify-write */
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mfsdram(DDR0_00, value);
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mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
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sync();
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eieio();
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return ret;
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}
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int ecc_post_test (int flags)
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{
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int ret = 0;
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unsigned long value;
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unsigned long iaddr;
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sync();
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eieio();
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mfsdram(DDR0_22, value);
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if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) {
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debug("SDRAM ECC not enabled, skipping ECC POST.\n");
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return 0;
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}
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/* mask all int */
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mfsdram(DDR0_01, value);
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mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK)
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| DDR0_01_INT_MASK_ALL_OFF);
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/* clear error status */
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mfsdram(DDR0_00, value);
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mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
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for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) {
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ret = test_ecc(iaddr);
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if (ret)
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break;
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}
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/*
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* Clear possible errors resulting from ECC testing.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return ret;
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}
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#endif /* CONFIG_POST & CFG_POST_ECC */
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#endif /* defined(CONFIG_POST) && ... */
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