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7f1a30fdeb
This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint ipi driver to support ACLINT mswi device, by checking the per-driver data field of the ACLINT mtimer driver to determine whether a syscon based approach needs to be taken to get the base address of the ACLINT mswi device. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
78 lines
1.6 KiB
C
78 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*
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* U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
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* The CLINT block holds memory-mapped control and status registers
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* associated with software and timer interrupts.
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*/
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#include <common.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/syscon.h>
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#include <linux/err.h>
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/* MSIP registers */
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#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
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DECLARE_GLOBAL_DATA_PTR;
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int riscv_init_ipi(void)
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{
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int ret;
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struct udevice *dev;
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ret = uclass_get_device_by_driver(UCLASS_TIMER,
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DM_DRIVER_GET(sifive_clint), &dev);
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if (ret)
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return ret;
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if (dev_get_driver_data(dev) != 0)
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gd->arch.clint = dev_read_addr_ptr(dev);
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else
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gd->arch.clint = syscon_get_first_range(RISCV_SYSCON_CLINT);
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if (!gd->arch.clint)
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return -EINVAL;
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return 0;
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}
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int riscv_send_ipi(int hart)
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{
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writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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int riscv_clear_ipi(int hart)
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{
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writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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int riscv_get_ipi(int hart, int *pending)
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{
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*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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static const struct udevice_id riscv_aclint_swi_ids[] = {
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{ .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_CLINT },
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{ }
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};
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U_BOOT_DRIVER(riscv_aclint_swi) = {
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.name = "riscv_aclint_swi",
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.id = UCLASS_SYSCON,
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.of_match = riscv_aclint_swi_ids,
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.flags = DM_FLAG_PRE_RELOC,
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};
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