mirror of
https://github.com/AsahiLinux/u-boot
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1e94b46f73
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
745 lines
22 KiB
C
745 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Marvell International Ltd.
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/ptrace.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/delay.h>
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#include <linux/printk.h>
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#include "comphy_core.h"
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#include "sata.h"
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#include "utmi_phy.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* Firmware related definitions used for SMC calls */
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#define MV_SIP_COMPHY_POWER_ON 0x82000001
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#define MV_SIP_COMPHY_POWER_OFF 0x82000002
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#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
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#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
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/* Used to distinguish between different possible callers (U-Boot/Linux) */
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#define COMPHY_CALLER_UBOOT (0x1 << 21)
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#define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12)
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#define COMPHY_FW_FORMAT(mode, idx, speeds) \
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(((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
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#define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \
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(COMPHY_CALLER_UBOOT | ((pcie_width) << 18) | \
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((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds))
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/* Invert polarity are bits 1-0 of the mode */
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#define COMPHY_FW_SATA_FORMAT(mode, invert) \
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((invert) | COMPHY_FW_MODE_FORMAT(mode))
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#define COMPHY_SATA_MODE 0x1
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#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
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#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
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#define COMPHY_USB3H_MODE 0x4
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#define COMPHY_USB3D_MODE 0x5
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#define COMPHY_PCIE_MODE 0x6
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#define COMPHY_RXAUI_MODE 0x7
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#define COMPHY_XFI_MODE 0x8
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#define COMPHY_SFI_MODE 0x9
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#define COMPHY_USB3_MODE 0xa
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#define COMPHY_AP_MODE 0xb
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/* Comphy unit index macro */
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#define COMPHY_UNIT_ID0 0
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#define COMPHY_UNIT_ID1 1
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#define COMPHY_UNIT_ID2 2
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#define COMPHY_UNIT_ID3 3
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struct utmi_phy_data {
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void __iomem *utmi_pll_addr;
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void __iomem *utmi_base_addr;
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void __iomem *usb_cfg_addr;
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void __iomem *utmi_cfg_addr;
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u32 utmi_phy_port;
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};
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static u32 polling_with_timeout(void __iomem *addr, u32 val,
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u32 mask, unsigned long usec_timout)
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{
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u32 data;
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do {
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udelay(1);
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data = readl(addr) & mask;
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} while (data != val && --usec_timout > 0);
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if (usec_timout == 0)
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return data;
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return 0;
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}
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static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
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u32 lane, u32 mode)
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{
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struct pt_regs pregs = {0};
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pregs.regs[0] = function_id;
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pregs.regs[1] = (unsigned long)comphy_base_addr;
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pregs.regs[2] = lane;
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pregs.regs[3] = mode;
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smc_call(&pregs);
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/*
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* TODO: Firmware return 0 on success, temporary map it to u-boot
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* convention, but after all comphy will be reworked the convention in
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* u-boot should be change and this conversion removed
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*/
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return pregs.regs[0] ? 0 : 1;
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}
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/* This function performs RX training for all FFE possible values.
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* We get the result for each FFE and eventually the best FFE will
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* be used and set to the HW.
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*
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* Return '1' on succsess.
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* Return '0' on failure.
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*/
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int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
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u32 lane)
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{
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int ret;
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u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
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debug_enter();
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if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
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pr_err("Comphy %d isn't configured to SFI\n", lane);
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return 0;
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}
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/* Mode is not relevant for xfi training */
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ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN,
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ptr_chip_cfg->comphy_base_addr, lane, 0);
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debug_exit();
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return ret;
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}
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static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
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void __iomem *comphy_base_addr, int cp_index,
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u32 type)
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{
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u32 mask, data, i, ret = 1;
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void __iomem *sata_base = NULL;
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int sata_node = -1; /* Set to -1 in order to read the first sata node */
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debug_enter();
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/*
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* Assumption - each CP has only one SATA controller
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* Calling fdt_node_offset_by_compatible first time (with sata_node = -1
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* will return the first node always.
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* In order to parse each CPs SATA node, fdt_node_offset_by_compatible
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* must be called again (according to the CP id)
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*/
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for (i = 0; i < (cp_index + 1); i++)
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sata_node = fdt_node_offset_by_compatible(
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gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
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if (sata_node == 0) {
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pr_err("SATA node not found in FDT\n");
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return 0;
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}
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sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
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gd->fdt_blob, sata_node, "reg", 0, NULL, true);
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if (sata_base == NULL) {
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pr_err("SATA address not found in FDT\n");
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return 0;
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}
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debug("SATA address found in FDT %p\n", sata_base);
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debug("stage: MAC configuration - power down comphy\n");
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/*
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* MAC configuration powe down comphy use indirect address for
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* vendor spesific SATA control register
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*/
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reg_set(sata_base + SATA3_VENDOR_ADDRESS,
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SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
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SATA3_VENDOR_ADDR_MASK);
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/* SATA 0 power down */
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mask = SATA3_CTRL_SATA0_PD_MASK;
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data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
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/* SATA 1 power down */
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mask |= SATA3_CTRL_SATA1_PD_MASK;
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data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
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/* SATA SSU disable */
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mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
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data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
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/* SATA port 1 disable */
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mask |= SATA3_CTRL_SATA_SSU_MASK;
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data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
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reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
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ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, comphy_base_addr, lane, type);
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/*
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* MAC configuration power up comphy - power up PLL/TX/RX
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* use indirect address for vendor spesific SATA control register
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*/
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reg_set(sata_base + SATA3_VENDOR_ADDRESS,
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SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
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SATA3_VENDOR_ADDR_MASK);
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/* SATA 0 power up */
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mask = SATA3_CTRL_SATA0_PD_MASK;
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data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
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/* SATA 1 power up */
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mask |= SATA3_CTRL_SATA1_PD_MASK;
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data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
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/* SATA SSU enable */
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mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
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data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
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/* SATA port 1 enable */
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mask |= SATA3_CTRL_SATA_SSU_MASK;
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data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
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reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
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/* MBUS request size and interface select register */
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reg_set(sata_base + SATA3_VENDOR_ADDRESS,
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SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
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SATA3_VENDOR_ADDR_MASK);
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/* Mbus regret enable */
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reg_set(sata_base + SATA3_VENDOR_DATA,
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0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK);
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ret = comphy_smc(MV_SIP_COMPHY_PLL_LOCK, comphy_base_addr, lane, type);
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debug_exit();
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return ret;
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}
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static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
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void __iomem *usb_cfg_addr,
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void __iomem *utmi_cfg_addr,
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u32 utmi_phy_port)
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{
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u32 mask, data;
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debug_enter();
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debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n",
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utmi_index);
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/* Power down UTMI PHY */
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reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET,
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UTMI_PHY_CFG_PU_MASK);
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/*
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* If UTMI connected to USB Device, configure mux prior to PHY init
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* (Device can be connected to UTMI0 or to UTMI1)
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*/
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if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) {
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debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n",
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utmi_index);
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/* USB3 Device UTMI enable */
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mask = UTMI_USB_CFG_DEVICE_EN_MASK;
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data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
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/* USB3 Device UTMI MUX */
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mask |= UTMI_USB_CFG_DEVICE_MUX_MASK;
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data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET;
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reg_set(usb_cfg_addr, data, mask);
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}
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/* Set Test suspendm mode */
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mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK;
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data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET;
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/* Enable Test UTMI select */
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mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK;
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data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET;
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reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask);
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/* Wait for UTMI power down */
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mdelay(1);
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debug_exit();
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return;
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}
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static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr,
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void __iomem *utmi_base_addr,
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void __iomem *usb_cfg_addr,
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void __iomem *utmi_cfg_addr,
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u32 utmi_phy_port)
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{
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u32 mask, data;
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debug_exit();
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debug("stage: Configure UTMI PHY %d registers\n", utmi_index);
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/* Reference Clock Divider Select */
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mask = UTMI_PLL_CTRL_REFDIV_MASK;
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data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET;
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/* Feedback Clock Divider Select - 90 for 25Mhz*/
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mask |= UTMI_PLL_CTRL_FBDIV_MASK;
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data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET;
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/* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
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mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
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data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
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reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
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/* Impedance Calibration Threshold Setting */
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mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK;
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data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET;
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reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
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/* Start Impedance and PLL Calibration */
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mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK;
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data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET);
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mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK;
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data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET);
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reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
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/* Set LS TX driver strength coarse control */
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mask = UTMI_TX_CH_CTRL_AMP_MASK;
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data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
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mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
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data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
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mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
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data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
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reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
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/* Enable SQ */
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mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
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data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
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/* Enable analog squelch detect */
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mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
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data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
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mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK;
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data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET;
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reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
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/* Set External squelch calibration number */
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mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK;
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data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET;
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/* Enable the External squelch calibration */
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mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK;
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data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET;
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reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask);
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/* Set Control VDAT Reference Voltage - 0.325V */
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mask = UTMI_CHGDTC_CTRL_VDAT_MASK;
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data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET;
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/* Set Control VSRC Reference Voltage - 0.6V */
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mask |= UTMI_CHGDTC_CTRL_VSRC_MASK;
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data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET;
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reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask);
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debug_exit();
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return;
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}
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static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr,
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void __iomem *utmi_base_addr,
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void __iomem *usb_cfg_addr,
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void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
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{
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u32 data, mask, ret = 1;
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void __iomem *addr;
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debug_enter();
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debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n",
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utmi_index);
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/* Power UP UTMI PHY */
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reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET,
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UTMI_PHY_CFG_PU_MASK);
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/* Disable Test UTMI select */
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reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG,
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0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET,
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UTMI_CTRL_STATUS0_TEST_SEL_MASK);
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debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
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addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG;
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data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
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mask = data;
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data = polling_with_timeout(addr, data, mask, 100);
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if (data != 0) {
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pr_err("Impedance calibration is not done\n");
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debug("Read from reg = %p - value = 0x%x\n", addr, data);
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ret = 0;
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}
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data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK;
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mask = data;
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data = polling_with_timeout(addr, data, mask, 100);
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if (data != 0) {
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pr_err("PLL calibration is not done\n");
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debug("Read from reg = %p - value = 0x%x\n", addr, data);
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ret = 0;
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}
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addr = utmi_pll_addr + UTMI_PLL_CTRL_REG;
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data = UTMI_PLL_CTRL_PLL_RDY_MASK;
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mask = data;
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data = polling_with_timeout(addr, data, mask, 100);
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if (data != 0) {
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pr_err("PLL is not ready\n");
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debug("Read from reg = %p - value = 0x%x\n", addr, data);
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ret = 0;
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}
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if (ret)
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debug("Passed\n");
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else
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debug("\n");
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debug_exit();
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return ret;
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}
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/*
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* comphy_utmi_phy_init initialize the UTMI PHY
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* the init split in 3 parts:
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* 1. Power down transceiver and PLL
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* 2. UTMI PHY configure
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* 3. Power up transceiver and PLL
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* Note: - Power down/up should be once for both UTMI PHYs
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* - comphy_dedicated_phys_init call this function if at least there is
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* one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
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* legal
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*/
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static void comphy_utmi_phy_init(u32 utmi_phy_count,
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struct utmi_phy_data *cp110_utmi_data)
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{
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u32 i;
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debug_enter();
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/* UTMI Power down */
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for (i = 0; i < utmi_phy_count; i++) {
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comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr,
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cp110_utmi_data[i].usb_cfg_addr,
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cp110_utmi_data[i].utmi_cfg_addr,
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cp110_utmi_data[i].utmi_phy_port);
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}
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/* PLL Power down */
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debug("stage: UTMI PHY power down PLL\n");
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for (i = 0; i < utmi_phy_count; i++) {
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reg_set(cp110_utmi_data[i].usb_cfg_addr,
|
|
0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
|
|
}
|
|
/* UTMI configure */
|
|
for (i = 0; i < utmi_phy_count; i++) {
|
|
comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr,
|
|
cp110_utmi_data[i].utmi_base_addr,
|
|
cp110_utmi_data[i].usb_cfg_addr,
|
|
cp110_utmi_data[i].utmi_cfg_addr,
|
|
cp110_utmi_data[i].utmi_phy_port);
|
|
}
|
|
/* UTMI Power up */
|
|
for (i = 0; i < utmi_phy_count; i++) {
|
|
if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr,
|
|
cp110_utmi_data[i].utmi_base_addr,
|
|
cp110_utmi_data[i].usb_cfg_addr,
|
|
cp110_utmi_data[i].utmi_cfg_addr,
|
|
cp110_utmi_data[i].utmi_phy_port)) {
|
|
pr_err("Failed to initialize UTMI PHY %d\n", i);
|
|
continue;
|
|
}
|
|
printf("UTMI PHY %d initialized to ", i);
|
|
if (cp110_utmi_data[i].utmi_phy_port ==
|
|
UTMI_PHY_TO_USB3_DEVICE0)
|
|
printf("USB Device\n");
|
|
else
|
|
printf("USB Host%d\n",
|
|
cp110_utmi_data[i].utmi_phy_port);
|
|
}
|
|
/* PLL Power up */
|
|
debug("stage: UTMI PHY power up PLL\n");
|
|
for (i = 0; i < utmi_phy_count; i++) {
|
|
reg_set(cp110_utmi_data[i].usb_cfg_addr,
|
|
0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
|
|
}
|
|
|
|
debug_exit();
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* comphy_dedicated_phys_init initialize the dedicated PHYs
|
|
* - not muxed SerDes lanes e.g. UTMI PHY
|
|
*/
|
|
void comphy_dedicated_phys_init(void)
|
|
{
|
|
struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
|
|
int node = -1;
|
|
int node_idx;
|
|
int parent = -1;
|
|
|
|
debug_enter();
|
|
debug("Initialize USB UTMI PHYs\n");
|
|
|
|
for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) {
|
|
/* Find the UTMI phy node in device tree */
|
|
node = fdt_node_offset_by_compatible(gd->fdt_blob, node,
|
|
"marvell,mvebu-utmi-2.6.0");
|
|
if (node <= 0)
|
|
break;
|
|
|
|
/* check if node is enabled */
|
|
if (!fdtdec_get_is_enabled(gd->fdt_blob, node))
|
|
continue;
|
|
|
|
parent = fdt_parent_offset(gd->fdt_blob, node);
|
|
if (parent <= 0)
|
|
break;
|
|
|
|
/* get base address of UTMI PLL */
|
|
cp110_utmi_data[node_idx].utmi_pll_addr =
|
|
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
|
|
gd->fdt_blob, parent, "reg", 0, NULL, true);
|
|
if (!cp110_utmi_data[node_idx].utmi_pll_addr) {
|
|
pr_err("UTMI PHY PLL address is invalid\n");
|
|
continue;
|
|
}
|
|
|
|
/* get base address of UTMI phy */
|
|
cp110_utmi_data[node_idx].utmi_base_addr =
|
|
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
|
|
gd->fdt_blob, node, "reg", 0, NULL, true);
|
|
if (!cp110_utmi_data[node_idx].utmi_base_addr) {
|
|
pr_err("UTMI PHY base address is invalid\n");
|
|
continue;
|
|
}
|
|
|
|
/* get usb config address */
|
|
cp110_utmi_data[node_idx].usb_cfg_addr =
|
|
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
|
|
gd->fdt_blob, node, "reg", 1, NULL, true);
|
|
if (!cp110_utmi_data[node_idx].usb_cfg_addr) {
|
|
pr_err("UTMI PHY base address is invalid\n");
|
|
continue;
|
|
}
|
|
|
|
/* get UTMI config address */
|
|
cp110_utmi_data[node_idx].utmi_cfg_addr =
|
|
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
|
|
gd->fdt_blob, node, "reg", 2, NULL, true);
|
|
if (!cp110_utmi_data[node_idx].utmi_cfg_addr) {
|
|
pr_err("UTMI PHY base address is invalid\n");
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* get the port number (to check if the utmi connected to
|
|
* host/device)
|
|
*/
|
|
cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int(
|
|
gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
|
|
if (cp110_utmi_data[node_idx].utmi_phy_port ==
|
|
UTMI_PHY_INVALID) {
|
|
pr_err("UTMI PHY port type is invalid\n");
|
|
continue;
|
|
}
|
|
|
|
/* count valid UTMI unit */
|
|
node_idx++;
|
|
}
|
|
|
|
if (node_idx > 0)
|
|
comphy_utmi_phy_init(node_idx, cp110_utmi_data);
|
|
|
|
debug_exit();
|
|
}
|
|
|
|
int comphy_cp110_init_serdes_map(int node, struct chip_serdes_phy_config *cfg)
|
|
{
|
|
int lane, subnode;
|
|
|
|
cfg->comphy_lanes_count = fdtdec_get_int(gd->fdt_blob, node,
|
|
"max-lanes", 0);
|
|
if (cfg->comphy_lanes_count <= 0) {
|
|
printf("comphy max lanes is wrong\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
cfg->comphy_mux_bitcount = fdtdec_get_int(gd->fdt_blob, node,
|
|
"mux-bitcount", 0);
|
|
if (cfg->comphy_mux_bitcount <= 0) {
|
|
printf("comphy mux bit count is wrong\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
cfg->comphy_mux_lane_order = fdtdec_locate_array(gd->fdt_blob, node,
|
|
"mux-lane-order",
|
|
cfg->comphy_lanes_count);
|
|
|
|
lane = 0;
|
|
fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
|
|
/* Skip disabled ports */
|
|
if (!fdtdec_get_is_enabled(gd->fdt_blob, subnode))
|
|
continue;
|
|
|
|
cfg->comphy_map_data[lane].type =
|
|
fdtdec_get_int(gd->fdt_blob, subnode, "phy-type",
|
|
COMPHY_TYPE_INVALID);
|
|
|
|
if (cfg->comphy_map_data[lane].type == COMPHY_TYPE_INVALID) {
|
|
printf("no phy type for lane %d, setting lane as unconnected\n",
|
|
lane + 1);
|
|
continue;
|
|
}
|
|
|
|
cfg->comphy_map_data[lane].speed =
|
|
fdtdec_get_int(gd->fdt_blob, subnode, "phy-speed",
|
|
COMPHY_SPEED_INVALID);
|
|
|
|
cfg->comphy_map_data[lane].invert =
|
|
fdtdec_get_int(gd->fdt_blob, subnode, "phy-invert",
|
|
COMPHY_POLARITY_NO_INVERT);
|
|
|
|
cfg->comphy_map_data[lane].clk_src =
|
|
fdtdec_get_bool(gd->fdt_blob, subnode, "clk-src");
|
|
|
|
cfg->comphy_map_data[lane].end_point =
|
|
fdtdec_get_bool(gd->fdt_blob, subnode, "end_point");
|
|
|
|
lane++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
|
|
struct comphy_map *serdes_map)
|
|
{
|
|
struct comphy_map *ptr_comphy_map;
|
|
void __iomem *comphy_base_addr, *hpipe_base_addr;
|
|
u32 comphy_max_count, lane, id, ret = 0;
|
|
u32 pcie_width = 0;
|
|
u32 mode;
|
|
|
|
debug_enter();
|
|
|
|
comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
|
|
comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
|
|
hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
|
|
|
|
/* Check if the first 4 lanes configured as By-4 */
|
|
for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
|
|
lane++, ptr_comphy_map++) {
|
|
if (ptr_comphy_map->type != COMPHY_TYPE_PEX0)
|
|
break;
|
|
pcie_width++;
|
|
}
|
|
|
|
for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count;
|
|
lane++, ptr_comphy_map++) {
|
|
debug("Initialize serdes number %d\n", lane);
|
|
debug("Serdes type = 0x%x\n", ptr_comphy_map->type);
|
|
if (lane == 4) {
|
|
/*
|
|
* PCIe lanes above the first 4 lanes, can be only
|
|
* by1
|
|
*/
|
|
pcie_width = 1;
|
|
}
|
|
switch (ptr_comphy_map->type) {
|
|
case COMPHY_TYPE_UNCONNECTED:
|
|
mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT;
|
|
ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF,
|
|
ptr_chip_cfg->comphy_base_addr,
|
|
lane, mode);
|
|
case COMPHY_TYPE_IGNORE:
|
|
continue;
|
|
break;
|
|
case COMPHY_TYPE_PEX0:
|
|
case COMPHY_TYPE_PEX1:
|
|
case COMPHY_TYPE_PEX2:
|
|
case COMPHY_TYPE_PEX3:
|
|
mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
|
|
ptr_comphy_map->clk_src,
|
|
COMPHY_PCIE_MODE,
|
|
ptr_comphy_map->speed);
|
|
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
|
|
ptr_chip_cfg->comphy_base_addr, lane,
|
|
mode);
|
|
break;
|
|
case COMPHY_TYPE_SATA0:
|
|
case COMPHY_TYPE_SATA1:
|
|
mode = COMPHY_FW_SATA_FORMAT(COMPHY_SATA_MODE,
|
|
serdes_map[lane].invert);
|
|
ret = comphy_sata_power_up(lane, hpipe_base_addr,
|
|
comphy_base_addr,
|
|
ptr_chip_cfg->cp_index,
|
|
mode);
|
|
break;
|
|
case COMPHY_TYPE_USB3_HOST0:
|
|
case COMPHY_TYPE_USB3_HOST1:
|
|
mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE);
|
|
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
|
|
ptr_chip_cfg->comphy_base_addr, lane,
|
|
mode);
|
|
break;
|
|
case COMPHY_TYPE_USB3_DEVICE:
|
|
mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE);
|
|
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
|
|
ptr_chip_cfg->comphy_base_addr, lane,
|
|
mode);
|
|
break;
|
|
case COMPHY_TYPE_SGMII0:
|
|
case COMPHY_TYPE_SGMII1:
|
|
case COMPHY_TYPE_SGMII2:
|
|
/* Calculate SGMII ID */
|
|
id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0;
|
|
|
|
if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
|
|
debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
|
|
lane);
|
|
ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
|
|
}
|
|
|
|
mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id,
|
|
ptr_comphy_map->speed);
|
|
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
|
|
ptr_chip_cfg->comphy_base_addr, lane,
|
|
mode);
|
|
break;
|
|
case COMPHY_TYPE_SFI0:
|
|
case COMPHY_TYPE_SFI1:
|
|
/* Calculate SFI id */
|
|
id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
|
|
mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
|
|
ptr_comphy_map->speed);
|
|
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
|
|
ptr_chip_cfg->comphy_base_addr, lane, mode);
|
|
break;
|
|
case COMPHY_TYPE_RXAUI0:
|
|
case COMPHY_TYPE_RXAUI1:
|
|
mode = COMPHY_FW_MODE_FORMAT(COMPHY_RXAUI_MODE);
|
|
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
|
|
ptr_chip_cfg->comphy_base_addr, lane,
|
|
mode);
|
|
break;
|
|
default:
|
|
debug("Unknown SerDes type, skip initialize SerDes %d\n",
|
|
lane);
|
|
break;
|
|
}
|
|
if (ret == 0) {
|
|
/*
|
|
* If interface wans't initialized, set the lane to
|
|
* COMPHY_TYPE_UNCONNECTED state.
|
|
*/
|
|
ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED;
|
|
pr_err("PLL is not locked - Failed to initialize lane %d\n",
|
|
lane);
|
|
}
|
|
}
|
|
|
|
debug_exit();
|
|
return 0;
|
|
}
|