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12bbc0ba81
If without switch to main crystal oscillator, the sama5d3 SoC will use internal on chip RC oscillator. In order to get better accuracy, switch to main crystal oscillator. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
234 lines
9.4 KiB
C
234 lines
9.4 KiB
C
/*
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* [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
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*
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* Power Management Controller (PMC) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AT91_PMC_H
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#define AT91_PMC_H
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#ifdef __ASSEMBLY__
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#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20)
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#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28)
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#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c)
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#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30)
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#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68)
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#else
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#include <asm/types.h>
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typedef struct at91_pmc {
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u32 scer; /* 0x00 System Clock Enable Register */
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u32 scdr; /* 0x04 System Clock Disable Register */
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u32 scsr; /* 0x08 System Clock Status Register */
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u32 reserved0;
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u32 pcer; /* 0x10 Peripheral Clock Enable Register */
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u32 pcdr; /* 0x14 Peripheral Clock Disable Register */
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u32 pcsr; /* 0x18 Peripheral Clock Status Register */
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u32 uckr; /* 0x1C UTMI Clock Register */
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u32 mor; /* 0x20 Main Oscilator Register */
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u32 mcfr; /* 0x24 Main Clock Frequency Register */
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u32 pllar; /* 0x28 PLL A Register */
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u32 pllbr; /* 0x2C PLL B Register */
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u32 mckr; /* 0x30 Master Clock Register */
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u32 reserved1;
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u32 usb; /* 0x38 USB Clock Register */
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u32 reserved2;
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u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */
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u32 reserved3[4];
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u32 ier; /* 0x60 Interrupt Enable Register */
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u32 idr; /* 0x64 Interrupt Disable Register */
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u32 sr; /* 0x68 Status Register */
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u32 imr; /* 0x6C Interrupt Mask Register */
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u32 reserved4[4];
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u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */
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u32 reserved5[21];
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u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
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u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
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#ifdef CONFIG_SAMA5D3
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u32 reserved6[8];
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u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
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u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
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u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */
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u32 pcr; /* 0x10c Periperial Control Register */
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u32 ocr; /* 0x110 Oscillator Calibration Register */
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#else
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u32 reserved8[5];
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#endif
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} at91_pmc_t;
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#endif /* end not assembly */
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#define AT91_PMC_MOR_MOSCEN 0x01
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#define AT91_PMC_MOR_OSCBYPASS 0x02
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#define AT91_PMC_MOR_MOSCRCEN 0x08
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#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8)
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#define AT91_PMC_MOR_KEY(x) ((x & 0xff) << 16)
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#define AT91_PMC_MOR_MOSCSEL (1 << 24)
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#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
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#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
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#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
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#ifdef CONFIG_SAMA5D3
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#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18)
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#else
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#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
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#endif
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#define AT91_PMC_PLLAR_29 0x20000000
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#define AT91_PMC_PLLBR_USBDIV_1 0x00000000
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#define AT91_PMC_PLLBR_USBDIV_2 0x10000000
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#define AT91_PMC_PLLBR_USBDIV_4 0x20000000
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#define AT91_PMC_MCFR_MAINRDY 0x00010000
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#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF
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#define AT91_PMC_MCKR_CSS_SLOW 0x00000000
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#define AT91_PMC_MCKR_CSS_MAIN 0x00000001
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#define AT91_PMC_MCKR_CSS_PLLA 0x00000002
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#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
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#define AT91_PMC_MCKR_CSS_MASK 0x00000003
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#ifdef CONFIG_SAMA5D3
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#define AT91_PMC_MCKR_PRES_1 0x00000000
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#define AT91_PMC_MCKR_PRES_2 0x00000010
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#define AT91_PMC_MCKR_PRES_4 0x00000020
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#define AT91_PMC_MCKR_PRES_8 0x00000030
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#define AT91_PMC_MCKR_PRES_16 0x00000040
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#define AT91_PMC_MCKR_PRES_32 0x00000050
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#define AT91_PMC_MCKR_PRES_64 0x00000060
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#define AT91_PMC_MCKR_PRES_MASK 0x00000070
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#else
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#define AT91_PMC_MCKR_PRES_1 0x00000000
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#define AT91_PMC_MCKR_PRES_2 0x00000004
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#define AT91_PMC_MCKR_PRES_4 0x00000008
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#define AT91_PMC_MCKR_PRES_8 0x0000000C
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#define AT91_PMC_MCKR_PRES_16 0x00000010
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#define AT91_PMC_MCKR_PRES_32 0x00000014
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#define AT91_PMC_MCKR_PRES_64 0x00000018
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#define AT91_PMC_MCKR_PRES_MASK 0x0000001C
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#endif
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#ifdef CONFIG_AT91RM9200
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#define AT91_PMC_MCKR_MDIV_1 0x00000000
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#define AT91_PMC_MCKR_MDIV_2 0x00000100
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#define AT91_PMC_MCKR_MDIV_3 0x00000200
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#define AT91_PMC_MCKR_MDIV_4 0x00000300
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#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
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#else
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#define AT91_PMC_MCKR_MDIV_1 0x00000000
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#define AT91_PMC_MCKR_MDIV_2 0x00000100
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#ifdef CONFIG_SAMA5D3
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#define AT91_PMC_MCKR_MDIV_3 0x00000300
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#endif
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#define AT91_PMC_MCKR_MDIV_4 0x00000200
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#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
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#endif
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#define AT91_PMC_MCKR_PLLADIV_1 0x00000000
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#define AT91_PMC_MCKR_PLLADIV_2 0x00001000
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#define AT91_PMC_IXR_MOSCS 0x00000001
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#define AT91_PMC_IXR_LOCKA 0x00000002
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#define AT91_PMC_IXR_LOCKB 0x00000004
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#define AT91_PMC_IXR_MCKRDY 0x00000008
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#define AT91_PMC_IXR_LOCKU 0x00000040
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#define AT91_PMC_IXR_PCKRDY0 0x00000100
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#define AT91_PMC_IXR_PCKRDY1 0x00000200
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#define AT91_PMC_IXR_PCKRDY2 0x00000400
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#define AT91_PMC_IXR_PCKRDY3 0x00000800
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#define AT91_PMC_IXR_MOSCSELS 0x00010000
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */
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#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
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#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
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#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
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#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
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#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
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#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
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#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
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#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
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#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
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#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
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#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
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#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
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#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
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#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
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#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
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#define AT91_PMC_DIV (0xff << 0) /* Divider */
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#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
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#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
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#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
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#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
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#define AT91_PMC_USBDIV_1 (0 << 28)
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#define AT91_PMC_USBDIV_2 (1 << 28)
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#define AT91_PMC_USBDIV_4 (2 << 28)
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#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
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#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
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#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
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#define AT91_PMC_CSS_SLOW (0 << 0)
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#define AT91_PMC_CSS_MAIN (1 << 0)
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#define AT91_PMC_CSS_PLLA (2 << 0)
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#define AT91_PMC_CSS_PLLB (3 << 0)
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#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
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#define AT91_PMC_PRES_1 (0 << 2)
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#define AT91_PMC_PRES_2 (1 << 2)
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#define AT91_PMC_PRES_4 (2 << 2)
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#define AT91_PMC_PRES_8 (3 << 2)
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#define AT91_PMC_PRES_16 (4 << 2)
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#define AT91_PMC_PRES_32 (5 << 2)
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#define AT91_PMC_PRES_64 (6 << 2)
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#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
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#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
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#define AT91RM9200_PMC_MDIV_2 (1 << 8)
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#define AT91RM9200_PMC_MDIV_3 (2 << 8)
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#define AT91RM9200_PMC_MDIV_4 (3 << 8)
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#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
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#define AT91SAM9_PMC_MDIV_2 (1 << 8)
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#define AT91SAM9_PMC_MDIV_4 (2 << 8)
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#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
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#define AT91SAM9_PMC_MDIV_6 (3 << 8)
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#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
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#define AT91_PMC_PDIV_1 (0 << 12)
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#define AT91_PMC_PDIV_2 (1 << 12)
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#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
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#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
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#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */
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#define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */
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#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
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#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
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#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
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#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
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#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
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#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
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#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
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#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
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#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
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#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
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#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
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#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
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#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
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#endif
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